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    MC100LVEP Price and Stock

    Rochester Electronics LLC MC100LVEP16D

    LINE TRANSCEIVER
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    DigiKey MC100LVEP16D Tube 47,187 116
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    Rochester Electronics LLC MC100LVEP16DG

    DIFFERENTIAL DRIVER / RECEIVER
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    DigiKey MC100LVEP16DG Bulk 27,654 70
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    Rochester Electronics LLC MC100LVEP11DTG

    LOW SKEW CLOCK DRIVER, 100LVE SE
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    DigiKey MC100LVEP11DTG Bulk 25,173 53
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    Rochester Electronics LLC MC100LVEP11D

    IC CLK BUFFER 1:2 8SOIC
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    DigiKey MC100LVEP11D Tube 21,907 134
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    Rochester Electronics LLC MC100LVEP16DT

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    DigiKey MC100LVEP16DT Tube 21,175 116
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    MC100LVEP Datasheets (130)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    MC100LVEP05 On Semiconductor 2.5V / 3.3V ECL 2-Input Differential AND/NAND Original PDF
    MC100LVEP05DG On Semiconductor MC100LVEP05 - IC 100LVEP SERIES, 2-INPUT AND/NAND GATE, PDSO8, LEAD FREE, SOIC-8, Gate Original PDF
    MC100LVEP05DR2G On Semiconductor MC100LVEP05 - IC 100LVEP SERIES, 2-INPUT AND/NAND GATE, PDSO8, LEAD FREE, SOIC-8, Gate Original PDF
    MC100LVEP05DTG On Semiconductor 2.5V / 3.3V ECL 2-Input Differential AND/NAND Original PDF
    MC100LVEP05DTG On Semiconductor 2.5 V / 3.3 V ECL 2-Input Differential AND/NAND Original PDF
    MC100LVEP05DTR2G On Semiconductor 2.5V / 3.3V ECL 2-Input Differential AND/NAND Original PDF
    MC100LVEP05DTR2G On Semiconductor 2.5 V / 3.3 V ECL 2-Input Differential AND/NAND Original PDF
    MC100LVEP05MNTXG On Semiconductor 2.5V / 3.3V ECL 2-Input Differential AND/NAND Original PDF
    MC100LVEP05MNTXG On Semiconductor 2.5 V / 3.3 V ECL 2-Input Differential AND/NAND Original PDF
    MC100LVEP11 On Semiconductor 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer Original PDF
    MC100LVEP111 On Semiconductor 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Original PDF
    MC100LVEP111 On Semiconductor 2.5V - 3.3V 1:10 Differential ECL-PECL-HSTL Clock Driver Original PDF
    MC100LVEP111-D On Semiconductor 2.5V - 3.3V 1:10 Differential ECL-PECL-HSTL Clock Original PDF
    MC100LVEP111FA On Semiconductor 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver; Package: 32 LEAD LQFP 7x7, 0.8P; No of Pins: 32; Container: Tray; Qty per Container: 250 Original PDF
    MC100LVEP111FA On Semiconductor 2.5 V/3.3 V 1:10 Differential ECL/PECL/HSTL Clock Driver Original PDF
    MC100LVEP111FA On Semiconductor Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver Original PDF
    MC100LVEP111FAG On Semiconductor 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver; Package: 32 LEAD LQFP 7x7, 0.8P; No of Pins: 32; Container: Tray; Qty per Container: 250 Original PDF
    MC100LVEP111FAG On Semiconductor 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Original PDF
    MC100LVEP111FAR2 On Semiconductor 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver; Package: 32 LEAD LQFP 7x7, 0.8P; No of Pins: 32; Container: Tape and Reel; Qty per Container: 2000 Original PDF
    MC100LVEP111FAR2 On Semiconductor Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver Original PDF
    ...

    MC100LVEP Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    LVEP210

    Abstract: MC100 MC100EP210 MC100LVEP210
    Text: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is


    Original     		MC100LVEP210 MC100LVEP210 EP210 LVEP210 MC100LVEP210/D MC100 MC100EP210 PDF

    MC100LVEP14

    Abstract: 100 vp14 100VP14
    Text: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or


    Original     		MC100LVEP14 MC100LVEP14 LVEP14 MC100LVEP14/D 100 vp14 100VP14 PDF

    D1875

    Abstract: HVP16 KVP16 LVEL16 MC100LVEP16 MC10LVEP16
    Text: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16


    Original     		MC10LVEP16, MC100LVEP16 MC10/100LVEP16 LVEL16 LVEL16, LVEP16 MC10LVEP16/D D1875 HVP16 KVP16 LVEL16 MC100LVEP16 MC10LVEP16 PDF

    EP11

    Abstract: KVP11 MC100LVEP11 MC10LVEP11 930 TSSOP8
    Text: MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for


    Original     		MC10LVEP11, MC100LVEP11 MC10/100LVEP11 LVEP11 HVP11 MC10LVEP11/D EP11 KVP11 MC100LVEP11 MC10LVEP11 930 TSSOP8 PDF

    EP11

    Abstract: MC100LVEP11 MC10LVEP11 KU11 930 TSSOP8
    Text: MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for


    Original     		MC10LVEP11, MC100LVEP11 MC10/100LVEP11 LVEP11 HYP11 MC10LVEP11/D EP11 MC100LVEP11 MC10LVEP11 KU11 930 TSSOP8 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is


    Original     		MC100LVEP210 MC100LVEP210 EP210 LVEP210 MC100LVEP210/D PDF

    MC100LVEP14

    Abstract: TSSOP-20 MC100LVEP14DTG 0201 footprint
    Text: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or


    Original     		MC100LVEP14 MC100LVEP14 LVEP14 MC100LVEP14/D TSSOP-20 MC100LVEP14DTG 0201 footprint PDF

    Untitled

    Abstract: No abstract text available
    Text: MC100LVEP210 2.5V / 3.3VĄ1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single–ended if the VBB output is used. The


    Original     		MC100LVEP210 EP210 LVEP210 PDF

    100LVEP16

    Abstract: KVP16
    Text: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16


    Original     		MC10LVEP16, MC100LVEP16 MC10/100LVEP16 LVEL16 LVEL16, LVEP16 MC10LVEP16/D 100LVEP16 KVP16 PDF

    vbb vcc vee

    Abstract: No abstract text available
    Text: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is


    Original     		MC100LVEP210 EP210 LVEP210 MC100LVEP210/D vbb vcc vee PDF

    MC100

    Abstract: MC100EP05 MC100LVEP05
    Text: MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2-input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the


    Original     		MC100LVEP05 MC100LVEP05 MC100EP05 LVEL05 MC100LVEP05/D MC100 MC100EP05 PDF

    100LVEP34G

    Abstract: 6006B2 948F MC100LVEP34 TSSOP-16
    Text: MC100LVEP34 2.5V / 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common


    Original     		MC100LVEP34 MC100LVEP34 MC100LVEP34/D 100LVEP34G 6006B2 948F TSSOP-16 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC100LVEP34 2.5V / 3.3VĄECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common


    Original     		MC100LVEP34 r14525 MC100LVEP34/D PDF

    HVP16

    Abstract: KVP16 LVEL16 MC100LVEP16 MC10LVEP16 2015 soic8
    Text: MC10LVEP16, MC100LVEP16 2.5V / 3.3V ECL Differential Receiver/Driver Description MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 8 1 TSSOP−8 DT SUFFIX CASE 948R • 240 ps Propagation Delay • Maximum Frequency > 4 GHz Typical • PECL Mode Operating Range: VCC = 2.375 V to 3.8 V


    Original     		MC10LVEP16, MC100LVEP16 KVP16 HVP16 MC10/100LVEP16 MC10LVEP16/D HVP16 KVP16 LVEL16 MC100LVEP16 MC10LVEP16 2015 soic8 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single-ended if the VBB output is


    Original     		MC100LVEP210 MC100LVEP210 EP210 LVEP210 MC100LVEP210/D PDF

    948F

    Abstract: 100LVEP34 MC100LVEP34 MC100LVEP34D MC100LVEP34DR2 MC100LVEP34DT MC100LVEP34DTR2
    Text: MC100LVEP34 2.5V / 3.3VĄECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common


    Original     		MC100LVEP34 MC100LVEP34 r14525 MC100LVEP34/D 948F 100LVEP34 MC100LVEP34D MC100LVEP34DR2 MC100LVEP34DT MC100LVEP34DTR2 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC100LVEP14 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or


    Original     		MC100LVEP14 MC100LVEP14 LVEP14 MC100LVEP14/D PDF

    LVEP210

    Abstract: MC100 MC100EP210 MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2
    Text: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single-ended if the VBB output is


    Original     		MC100LVEP210 MC100LVEP210 EP210 LVEP210 MC100LVEP210/D MC100 MC100EP210 MC100LVEP210FA MC100LVEP210FAR2 PDF

    LVEP210

    Abstract: MC100 MC100EP210 MC100LVEP210 MC100LVEP210FA MC100LVEP210FAR2
    Text: MC100LVEP210 2.5V / 3.3VĄ1:5 Dual Differential ECL/PECL/HSTL Clock Driver The MC100LVEP210 is a low skew 1–to–5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single–ended if the VBB output is used. The


    Original     		MC100LVEP210 MC100LVEP210 EP210 LVEP210 r14525 MC100LVEP210/D MC100 MC100EP210 MC100LVEP210FA MC100LVEP210FAR2 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for


    Original     		MC10LVEP11, MC100LVEP11 MC10/100LVEP11 LVEP11 HVP11 KVP11 MC10LVEP11/D PDF

    QFN-32 footprint

    Abstract: MC100LVEP111 qfn32 tray MC100LVEP111FAR2 MC100LVEP111FARG MC100LVEP111MNG MC100LVEP111MNRG LVEP111 MC100LVEP111FA MC100LVEP111FAG
    Text: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or


    Original     		MC100LVEP111 1-to-10 LVEP111 MC100LVEP111/D QFN-32 footprint qfn32 tray MC100LVEP111FAR2 MC100LVEP111FARG MC100LVEP111MNG MC100LVEP111MNRG MC100LVEP111FA MC100LVEP111FAG PDF

    KVP05

    Abstract: ku05 26 MC100 MC100EP05 MC100LVEP05 KU05 MC100LVEP05DTG
    Text: MC100LVEP05 2.5V / 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With


    Original     		MC100LVEP05 MC100LVEP05 MC100EP05 LVEL05 KVP05 MC100LVEP05/D KVP05 ku05 26 MC100 MC100EP05 KU05 MC100LVEP05DTG PDF

    PIN CONFIGURATION IC 555

    Abstract: LQFP-32 footprint QFN-32 footprint lqfp-32 footprint layout LVEP111 MC100 MC100EP111 MC100LVEP111 QFN32 MC100LVEP111FARG
    Text: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or


    Original     		MC100LVEP111 MC100LVEP111 1-to-10 LVEP111 MC100LVEP111/D PIN CONFIGURATION IC 555 LQFP-32 footprint QFN-32 footprint lqfp-32 footprint layout MC100 MC100EP111 QFN32 MC100LVEP111FARG PDF

    LVEP111

    Abstract: MC100LVEP111FA MC100LVEP111FAR2 MC100 MC100LVEP111
    Text: MC100LVEP111 2.5V / 3.3VĄ1:10 Differential ECL/PECL/HSTL Clock Driver The MC100LVEP111 is a low skew 1–to–10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or


    Original     		MC100LVEP111 MC100LVEP111 LVEP111 r14525 MC100LVEP111/D MC100LVEP111FA MC100LVEP111FAR2 MC100 PDF