MARKING TP5C Search Results

ADV9502

Abstract: ep320Ipc TNPLD610 N85C220 D5AC312 EP320IDC npld610 EP320IPI EPX780LC84 N5C180
Contextual Info: April 4, 1995 Dear Customer: Effective July 1, 1995, Altera will transition from a dual mark, to a single mark for all products acquired from Intel. In addition, Altera will be converting solely to Altera ordering codes for these products See Table 1 . This change is cosmetic in nature and does not effect

marking TP5C

Abstract: TP5C TP2520 TP2520N8 TP2522 TP2522N8 TP2522ND
Contextual Info: TP2520 TP2522 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information RDS ON (max) VGS(th) (max) ID(ON) (min) TO-243AA* Die† -200V 12Ω -2.4V -0.75A TP2520N8 — -220V 12Ω -2.4V -0.75A TP2522N8 TP2522ND * Same as SOT-89. †

Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

A10150

Abstract: TO243AA TP2522 TP2522N8-G TP2522ND A101507
Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TO-243AA

Abstract: TN2520N8-G TP2520 tp5cw jedec package TO-243AA
Contextual Info: TP2520 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: TP2520 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2520N8-G

Contextual Info: TP2520 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2520

Abstract: TP2520N8 TP2522 TP2522N8 TP2522ND voltage drop circuit from 220V to 10V marking TP5C
Contextual Info: TP2520 TP2522 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information RDS ON (max) VGS(th) (max) ID(ON) (min) TO-243AA* Die† -200V 12Ω -2.4V -0.75A TP2520N8 — -220V 12Ω -2.4V -0.75A TP2522N8 TP2522ND * Same as SOT-89. †

Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2522ND

Abstract: TP2522 TP2522N8-G
Contextual Info: TP2522 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: Supertex inc. TP2522 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description ►► Low threshold -2.4V max. ►► High input impedance ►► Low input capacitance (125pF max.) ►► Fast switching speeds ►► Low on-resistance ►► Free from secondary breakdown

b0914

Contextual Info: TP2520 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: TP2520 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling

TP2520

Abstract: tp5cw TP5C
Contextual Info: TP2520 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: Supertex inc. TP2520 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description ►► Low threshold -2.4V max. ►► High input impedance ►► Low input capacitance (125pF max.) ►► Fast switching speeds ►► Low on-resistance ►► Free from secondary breakdown