MAIN BOARD PROBLEMS AND SOLUTION DIAGRAMS Search Results

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data

Contextual Info: ADS1 ADS1210 ADS1211 210 ADS 1211 ADS1 ADS1 211 ADS1 210 211 SBAS034B – JANUARY 1996 – REVISED SEPTEMBER 2005 24-Bit ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● DELTA-SIGMA A/D CONVERTER ● 23 BITS EFFECTIVE RESOLUTION AT 10Hz AND 20 BITS AT 1000Hz

SI3016

Contextual Info: TMS320C54V90 EMBEDDED V.90 MODEM DSP SPRS165F − JULY 2001 − REVISED OCTOBER 2003 D Provides Two-Chip Modem Solution D Data Rates from 300 bps to 56 Kbps D Data Modulation Standards D V.90, V.34, V.32bis, V.32, V.22bis, V.22, V.23, V.21 and V.23 Reversible Minitel , Bell 212,

Ap1c-d

Abstract: B2379 82378ZB
Contextual Info: intei 82378ZB SYSTEM I/O SIO AND 82379AB SYSTEM I/O APIC (SIO.A) Provides the Bridge Between the PCI Bus and ISA Bus 100% PCI and ISA Compatible — PCI and ISA Master/Slave Interface — Directly Drives 10 PCI Loads and 6 ISA Slots — PCI at 25 MHz and 33 MHz

Contextual Info: ß fö H O M O K lM lf intei M82380 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS High Performance 32-Bit DMA Controller — 40 MBytes/sec Maximum Data Transfer Rate at 20 MHz — 8 Independently Programmable Channels DRAM Refresh Controller

SPRC191

Abstract: SPRU430D
Contextual Info: TMS320F2808, TMS320F2806 TMS320F2801, UCD9501 Digital Signal Processors Data Manual Literature Number: SPRS230F October 2003 – Revised September 2005 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas