DS15BR400
Abstract: AN1194 DS15BR400EVK DS15BR401 TQFP-48
Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device
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DS15BR400/DS15BR401
DS15BR400/DS15BR401
DS15BR400
DS15BR401
AN1194
DS15BR400EVK
TQFP-48
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PDF
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DS15BR400
Abstract: DS15BR400EVK AN-1194 DS15BR401 TQFP-48
Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device
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Original
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DS15BR400/DS15BR401
DS15BR400/DS15BR401
DS15BR400
DS15BR401
DS15BR400EVK
AN-1194
TQFP-48
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PDF
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DS15BR400
Abstract: AN-1194 DS15BR400EVK DS15BR401 TQFP-48
Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device
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Original
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DS15BR400/DS15BR401
DS15BR400/DS15BR401
DS15BR400
DS15BR401
AN-1194
DS15BR400EVK
TQFP-48
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PDF
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DS15BR400
Abstract: AN-1194 DS15BR400EVK DS15BR401 TQFP-48
Text: DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis General Description Features The DS15BR400/DS15BR401 are four channel LVDS buffer/ repeaters capable of datarates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device
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Original
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DS15BR400/DS15BR401
DS15BR400/DS15BR401
DS15BR400
DS15BR401
AN-1194
DS15BR400EVK
TQFP-48
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PDF
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DS90LV047A
Abstract: MAX9122 MAX9123 MAX9178 MAX9178ETE MAX9178EUE
Text: 19-2856; Rev 0; 4/03 Quad LVDS Line Driver with High-ESD Tolerance and Flow-Through Pinout The MAX9178 operates from a single +3.3V supply, and is available in a 16-pin TSSOP and 16-pin thin QFN package with exposed pad. The MAX9178 is specified for operation from -40°C to +85°C.
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MAX9178
16-pin
DS90LV047A
MAX9123
400Mbps
250ps
TIA/EIA-644
MAX9178
MAX9122
MAX9123
MAX9178ETE
MAX9178EUE
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PDF
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Untitled
Abstract: No abstract text available
Text: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet October 24, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max
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UT54LVDS218
48-lead
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PDF
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Untitled
Abstract: No abstract text available
Text: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet October 4, 2001 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max
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UT54LVDS218
48-lead
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PDF
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82GM45
Abstract: ROBO-8719VG2AR
Text: ROBO-8719VG2AR Intel latest 45nm Core TM 2 Duo or Celeron® M processor based on PICMG SBC with DDR2 SDRAM, VGA, Dual Gigabit Ethernet and Audio One RS232 port Additional power source FDD Dual 240-pin DDR2 DIMM sockets One RS232/422/485 selectable port
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ROBO-8719VG2AR
RS232
240-pin
RS232/422/485
ROBO-8719VG2AR
256MB
2048x1536
24-bit
SBC-ROBO-8719VG2AR
82GM45
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PDF
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54LVDS218
Abstract: LVDS217
Text: Standard Products UT54LVDS218 Deserializer Advanced Data Sheet February, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max
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Original
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UT54LVDS218
48-lead
54LVDS218
LVDS217
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PDF
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5962 38535
Abstract: No abstract text available
Text: Standard Products UT54LVDS218 Deserializer Data Sheet May 24, 2002 FEATURES INTRODUCTION q q q q q 15 to 50MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The UT54LVDS218 Deserializer converts the three LVDS data
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UT54LVDS218
50MHz
50MHz,
48-lead
5962 38535
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PDF
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54LVDS218
Abstract: UT54LVDS218 LVDS217 marking RAD
Text: Standard Products UT54LVDS218 Deserializer Data Sheet April, 2002 FEATURES INTRODUCTION q q q q q 15 to 75 MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The UT54LVDS218 Deserializer converts the three LVDS data
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Original
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UT54LVDS218
48-lead
54LVDS218
LVDS217
marking RAD
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PDF
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Untitled
Abstract: No abstract text available
Text: Standard Products UT54LVDS218 Deserializer Data Sheet June 24, 2002 FEATURES INTRODUCTION q q q q q 15 to 50MHz shift clock support 50% duty cycle on receiver output clock Low power consumption Cold sparing all pins Power-down mode <200µW max The UT54LVDS218 Deserializer converts the three LVDS data
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UT54LVDS218
50MHz
50MHz,
48-lead
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PDF
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MAX5881
Abstract: MAX19693 MAX19692 SLVS ST max19693 datasheet MAX19588 SLVS max2015 MAX1436 MAX19515
Text: High-Speed ADCs, DACs, & AFEs 11th Edition September 2008 Industry’s lowest power, dual-channel 10-bit, 130Msps ADC has superior dynamic performance Extensive feature set minimizes external component count The MAX19517 ADC is a member of Maxim’s pin-compatible family of ultra-low-power, dual-channel
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10-bit,
130Msps
MAX19517
MAX19517
ADC/DAC/AFE-11
MAX5881
MAX19693
MAX19692
SLVS ST
max19693 datasheet
MAX19588
SLVS
max2015
MAX1436
MAX19515
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PDF
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MAX9179ETE
Abstract: MAX9179EUE DS90LV048A IN47 MAX9121 MAX9179
Text: 19-2752; Rev 0; 2/03 Quad LVDS Receiver with Hysteresis Features ♦ Guaranteed 400Mbps Data Rate The MAX9179 operates from a single 3.3V supply, and is specified for operation from -40°C to +85°C. The device is offered in 16-pin TSSOP and thin QFN packages.
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400Mbps
MAX9179
16-pin
MAX9121
DS90LV048A
IEC61000-4-2
100mV
TIA/EIA-644
MAX9179
MAX9179ETE
MAX9179EUE
DS90LV048A
IN47
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PDF
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Untitled
Abstract: No abstract text available
Text: SCAN90004 www.ti.com SNLS182P – MAY 2005 – REVISED APRIL 2013 SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis Check for Samples: SCAN90004 FEATURES DESCRIPTION • • The SCAN90004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flowthrough pinout minimize internal device jitter and
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SCAN90004
SNLS182P
SCAN90004
DS90LV004
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PDF
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IEEE1149
Abstract: No abstract text available
Text: SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis and IEEE 1149.6 General Description Features The SCAN90004 is a four channel 1.5 Gbps LVDS buffer/ repeater. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout,
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SCAN90004
IEEE1149
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PDF
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Untitled
Abstract: No abstract text available
Text: 19-1909; Rev 0; 6/01 KIT ATION EVALU LE B A IL A AV Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout _Features ♦ Integrated Termination Eliminates Four External Resistors MAX9122 The MAX9121/MAX9122 accept four LVDS differential
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MAX9122)
MAX9121/MAX9122
MAX9122
MAX9121
500Mbps
MAX9121/MAX9122
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PDF
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IN4107
Abstract: max9122
Text: 19-1909; Rev 0; 6/01 KIT ATION EVALU LE B A IL A AV Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout _Features ♦ Integrated Termination Eliminates Four External Resistors MAX9122 ♦ Flow-Through Pinout
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MAX9121/MAX9122
500Mbps
250MHz)
MAX9122
MAX9121/MAX9122
IN4107
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PDF
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maxim 1909
Abstract: DS90LV048A MAX9121 MAX9121ESE MAX9121EUE MAX9122 MAX9123
Text: 19-1909; Rev 0; 6/01 KIT ATION EVALU LE B A IL A AV Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout _Features ♦ Integrated Termination Eliminates Four External Resistors MAX9122 ♦ Flow-Through Pinout
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MAX9122)
DS90LV048A
500Mbps
300ps
TIA/EIA-644
MAX9121EUE
MAX9121ESE
MAX9122EUE
MAX9122ESE
MAX9121/MAX9122
maxim 1909
DS90LV048A
MAX9121
MAX9121ESE
MAX9121EUE
MAX9122
MAX9123
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PDF
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3mm ir receiver
Abstract: ANSI/TIA/EIA-644 Single LVDS Line transmitter in SC70 DS90LV048A MAX9121 MAX9122 MAX9123 MAX9173 MAX9173ESE MAX9173ETE
Text: 19-2595; Rev 0; 10/02 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe Features ♦ Accepts LVDS and LVPECL Inputs ♦ Fully Compatible with DS90LV048A ♦ Low 1.0mA max Disable Supply Current ♦ In-Path Fail-Safe Circuitry ♦ Flow-Through Pinout
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Original
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DS90LV048A
500Mbps
400ps
TIA/EIA-644
MAX9173EUE
MAX9173ESE
MAX9173ETE*
MS012
3mm ir receiver
ANSI/TIA/EIA-644
Single LVDS Line transmitter in SC70
DS90LV048A
MAX9121
MAX9122
MAX9123
MAX9173
MAX9173ESE
MAX9173ETE
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PDF
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MAX9110
Abstract: MAX9112 MAX9159 MAX9159ESA SN65LVDS9637 "DUAL LVDS"
Text: 19-2274; Rev 0; 1/02 Dual LVDS Line Receiver Features ♦ Pin Compatible with SN65LVDS9637 ♦ Fail-Safe Circuit Sets Output High for Undriven Inputs ♦ Conforms to ANSI TIA/EIA-644 Standard ♦ Single 3.3V Supply ♦ Designed for Data Rates up to 400Mbps
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SN65LVDS9637
TIA/EIA-644
400Mbps
100mV
200MHz
MAX9159ESA
MAX9159
MAX9110
MAX9112
MAX9159
MAX9159ESA
SN65LVDS9637
"DUAL LVDS"
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PDF
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ANSI/TIA/EIA-644
Abstract: MAX9110 MAX9112 MAX9159 MAX9159ESA SN65LVDS9637 LVDS 30 pin cable
Text: 19-2274; Rev 0; 1/02 Dual LVDS Line Receiver Features ♦ Pin Compatible with SN65LVDS9637 ♦ Fail-Safe Circuit Sets Output High for Undriven Inputs ♦ Conforms to ANSI TIA/EIA-644 Standard ♦ Single 3.3V Supply ♦ Designed for Data Rates up to 400Mbps
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Original
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SN65LVDS9637
TIA/EIA-644
400Mbps
100mV
200MHz
MAX9159ESA
MAX9159
ANSI/TIA/EIA-644
MAX9110
MAX9112
MAX9159
MAX9159ESA
SN65LVDS9637
LVDS 30 pin cable
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PDF
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Untitled
Abstract: No abstract text available
Text: 19-2595; Rev 0; 10/02 Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe The MAX9173 accepts four LVDS differential inputs and translates them to LVCMOS/LVTTL outputs. The MAX9173 inputs are high impedance and require an external termination resistor when used in a point-topoint connection.
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Original
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MAX9173
MS012
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PDF
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Untitled
Abstract: No abstract text available
Text: DS90LV047A www.ti.com SNLS044B – MAY 2004 – REVISED MAY 2004 DS90LV047A 3V LVDS Quad CMOS Differential Line Driver Check for Samples: DS90LV047A FEATURES 1 • • • • • • • • 23 >400 Mbps 200 MHz switching rates Flow-through pinout simplifies PCB layout
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Original
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DS90LV047A
SNLS044B
DS90LV047A
TIA/EIA-644
DS90Li
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PDF
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