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    LSI LEVEL TRANSLATION Search Results

    LSI LEVEL TRANSLATION Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74LV4T126FK Toshiba Electronic Devices & Storage Corporation Level shifter, Unidirectional, 1-Bit x 4 Single Supply Bus Buffer, US14, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74LV4T125FK Toshiba Electronic Devices & Storage Corporation Level shifter, Unidirectional, 1-Bit x 4 Single Supply Bus Buffer, US14, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1T04NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Inverter with Level Shifting, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer with Level Shifting, SOT-765 (US8), 2 in 1, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer with Level Shifting, SOT-765 (US8), 2 in 1, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation

    LSI LEVEL TRANSLATION Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    bpw 50

    Abstract: No abstract text available
    Text: Using PrimeTime in LSI Logic’s FlexStream Design Flow Robert Landy Yoon Kim LSI Logic Milpitas, CA landy@lsil.com ykim@lsil.com Abstract For large or complex System-on-a-Chip designs, which often consist of over one million gates, full chip gate-level dynamic simulation is becoming increasingly time consuming and verification


    Original     		PDF

    Hitachi DSAUTAZ006

    Abstract: No abstract text available
    Text: Section 1 Overview The SH7706 is a RISC microprocessor that integrates a Hitachi-original RISC-type SuperH architecture SH-3 CPU as its core that has peripheral functions required for system configuration. The CPU of this LSI has upper compatibility with the SH-1 and SH-2 at object code level. This


    Original     		SH7706 128-entry 32-bit 10-bitits Hitachi DSAUTAZ006 PDF

    hta08

    Abstract: HTA06 HTD12 HTD24 IC 501 CBA07 CBD70 CBD50 HTA09 HTD08
    Text: データ・シート MOS 集積回路 MOS Integrated Circuit PD98412 1.5G ATM Switch LSI μPD98412（NEASCOT-X15 ）は，ATM スイッチ機能を 1 チップに搭載した LSI で，UTOPIA Level 2 インタフェー スを持ち，マルチ PHY 接続を利用して 30x30 回線をスイッチングできます。また，共有バッファ方式ノンブロッキ


    Original     		PD98412 NEASCOT-X15TM PD98412 S14169J 16K/32K/64K 8K/25 6K/51 S14237JJ2V0DS00 hta08 HTA06 HTD12 HTD24 IC 501 CBA07 CBD70 CBD50 HTA09 HTD08 PDF

    LSI CMOS GATE ARRAY

    Abstract: LSI Logic ASIC
    Text: CMOS ASIC Translation Of Existing ASIC Designs Introduction It has only been in the last few years that designers and users of application specific integrated circuits ASIC have been able to obtain additional sources for these types of integrated circuits.


    Original     		PDF

    LSI CMOS GATE ARRAY

    Abstract: asic design flow asic flow lsi logic asic operate database application
    Text: CMOS ASIC Translation Of Existing ASIC Designs Introduction It has only been in the last few years that designers and users of application specific integrated circuits ASIC have been able to obtain additional sources for these types of integrated circuits. The


    Original     		PDF

    LSI Logic

    Abstract: primetime si user guide 74426 LSI logic array components lsi ndl
    Text: Lr Lecture 1 Chip Planning Tools Flow and Licensing 06-00 1.1 1 We Will Discuss… • • • • • • Avant! Tools Overview High Level Planet -PL Flow Detailed Chip Planning Tools Flow Design Methodology Flow Licensing Issues lsidesmgr & Design Setup


    Original     		G10/G11/G12) LSI Logic primetime si user guide 74426 LSI logic array components lsi ndl PDF

    IB14

    Abstract: timing circuit 4536 4536 circuits 29736
    Text: G12 -p Ultra160 SCSI Transceiver, 160 Mbytes/s SCSI Bus Transfer Rate Datasheet The Ultra160 SCSI1 transceiver and associated cells provide up to 160 Mbytes/s of on-chip input/output I/O signaling for application-specific integrated circuit (ASIC) chips implemented in the


    Original     		G12TM-p Ultra160 scsiulvdls33 scsibiasls33 ddrvscsi5ls33 IB14 timing circuit 4536 4536 circuits 29736 PDF

    LSI LOGIC

    Abstract: v 4520 lsi level translation
    Text: G12 -p bd4f5fs60ls33 4 mA, 60 MHz, 5-Volt Tolerant, Fail-Safe I/O Buffer Datasheet The bd4f5fs60ls33 bidirectional buffer cell Figure 1 provides up to 60 MHz off-chip input/output (I/O) signaling for application-specific integrated circuit (ASIC) chips implemented in the LSI Logic G12™-p


    Original     		G12TM-p bd4f5fs60ls33 bd4f5fs60ls33 G12TM-p I15044 DB08-000160-00 LSI LOGIC v 4520 lsi level translation PDF

    IB39

    Abstract: ATA100 ATA-100 29736
    Text: G12 -p ATA100 3.3 V, 5-Volt Tolerant, Fail-Safe I/O Buffer Datasheet The ATA100 I/O buffer provides on-chip input/output I/O signaling for application-specific integrated circuit (ASIC) chips implemented in the LSI Logic G12™-p 0.13 µm process technology. The buffer operates at


    Original     		G12TM-p ATA100 ATA100 ata100f5fsls33 atabiasls33 atacornerls33 atapvddio33 IB39 ATA-100 29736 PDF

    ARM926EJ-S Implementation Guide

    Abstract: ARM926EJ-S verilog coding for APB bridge state machine for ahb to apb bridge 8 pin AHB ARM926E-JS verilog code for amba ahb master AMBA 2.0 AHB to APB BUS Bridge verilog code AMBA AHB to APB BUS Bridge verilog code ARM926EJ-S jtag
    Text: DATASHEET 0.11 µm Processor System for ARM926EJ-S cw001200_agflxr_2_0 February 2005 Preliminary DB08-000261-01 This document is preliminary. As such, it contains data derived from functional simulations and performance estimates. LSI Logic has not verified either the


    Original     		ARM926EJ-STM cw001200 DB08-000261-01 cw001124 ARM926EJ-S Implementation Guide ARM926EJ-S verilog coding for APB bridge state machine for ahb to apb bridge 8 pin AHB ARM926E-JS verilog code for amba ahb master AMBA 2.0 AHB to APB BUS Bridge verilog code AMBA AHB to APB BUS Bridge verilog code ARM926EJ-S jtag PDF

    YUV422

    Abstract: YUV422 yuv420 RGB565 RGB666 wiring diagram for LCS YUV420
    Text: Ordering number : EN*8010 LC822142N CMOS IC CCD-LCD Interface ASIC Overview LC822142N is a chip which compresses and expands the image inputted from the CCD/CMOS by JPEG format, interfacing the LCD controller equipped with built-in CCD/CMOS sensor module and display memory for DSCPHONEs. Since the I2C master device circuit is embedded in the IC and the signal required for the CCD/CMOS module


    Original     		LC822142N LC822142N YUV422 YUV422 yuv420 RGB565 RGB666 wiring diagram for LCS YUV420 PDF

    DB14-000174

    Abstract: Fusion-MPT Message Passing Interface MPI specification DB14-000174-00 LSIFC919 AA13 PAR64 PC01 fixed burst PBSRAM Fusion-MPT Message Passing Interface Specification LSI Message Passing Interface MPI specification
    Text: TECHNICAL MANUAL LSIFC919 Single Channel Fibre Channel I/O Processor Revision 2.1 October 2002 DB14-000151-02 Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:


    Original     		LSIFC919 DB14-000151-02 DB14-000174 Fusion-MPT Message Passing Interface MPI specification DB14-000174-00 LSIFC919 AA13 PAR64 PC01 fixed burst PBSRAM Fusion-MPT Message Passing Interface Specification LSI Message Passing Interface MPI specification PDF

    Untitled

    Abstract: No abstract text available
    Text: 1/4 ● Structure ● Product Silicon Monolithic Integrated Circuit 7 x 7 Matrix LED DRIVER for Mobile Phone ● Type ● Figure BH6948GU 1. 2. 3. 4. 5. 6. Highly effective Charge Pump circuit that can be switched 1 time, 1.5 times, and 2 times pressure automatically. 190mA / MAX


    Original     		BH6948GU 190mA 31mA/ch, 62pin PDF

    Fusion-MPT Message Passing Interface MPI specification

    Abstract: Fusion-MPT Message Passing Interface Specification LSI Message Passing Interface MPI specification DB14-000174 DB14-000174-00 LSIFC929 PAR64 PC01 LSI "message passing interface specification" Fusion-MPT Message Passing Interface Specification doorbell
    Text: Technical Manual LSIFC929 Dual Channel Fibre Channel I/O Processor Revision 2.0 August 2001 S14073 Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: 1. 2. This device may not cause harmful interference, and


    Original     		LSIFC929 S14073 Fusion-MPT Message Passing Interface MPI specification Fusion-MPT Message Passing Interface Specification LSI Message Passing Interface MPI specification DB14-000174 DB14-000174-00 PAR64 PC01 LSI "message passing interface specification" Fusion-MPT Message Passing Interface Specification doorbell PDF

    2n2222 -331

    Abstract: 2n2222 - 331 str11 402ZX 2n2222 a 331 402Z EB402 LSI402Z LSI402ZX ZSP400
    Text: Using the Host Port Interface on the LSI402Z/LSI402ZX DSPs Application Note Contents 1 2 3 4 5 Appendix A DB06-000271-00 Host A.1 A.2 A.3 A.4 Port Functionality Uses of the HPI 2.1 Boot Loader 2.2 Data Read/Write 2.3 DMA Memory Access 2.4 Debugging Code Examples


    Original     		LSI402Z/LSI402ZX DB06-000271-00 LSI402ZX 2n2222 -331 2n2222 - 331 str11 402ZX 2n2222 a 331 402Z EB402 LSI402Z ZSP400 PDF

    DB14-000174-00

    Abstract: DB14-000174 Fusion-MPT Message Passing Interface MPI specification LSIFC919 LSIFC929 PAR64 PC01 ACK64 Fusion-MPT Message Passing Interface Specification
    Text: Technical Manual LSIFC919 Single Channel Fibre Channel I/O Processor Revision 2.0 October 2001 DB15-000151-01 Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:


    Original     		LSIFC919 DB15-000151-01 DB14-000174-00 DB14-000174 Fusion-MPT Message Passing Interface MPI specification LSIFC929 PAR64 PC01 ACK64 Fusion-MPT Message Passing Interface Specification PDF

    SH7706

    Abstract: 32-bit microprocessor pipeline architecture
    Text: Section 1 Overview The SH7706 is a RISC microprocessor that integrates a Renesas Technology-original RISC-type SuperH architecture SH-3 CPU as its core that has peripheral functions required for system configuration. The CPU of this LSI has upper compatibility with the SH-1 and SH-2 at object code


    Original     		SH7706 128-entry 32-bit 10-bit 32-bit microprocessor pipeline architecture PDF

    lsi svm

    Abstract: No abstract text available
    Text: Product Brief LSI StoreAge SVM — Storage Virtualization Manager Highlights With its innovative, “Split-Path” architecture, StoreAge SVM provides centrally managed storage pooling and virtual volume allocations for the entire SAN. n Split-Path Architecture


    Original     		PDF

    reco relay

    Abstract: UDN2580A UDN6118A-1 udn2983a UDN2983 ULN2804A
    Text: APPLICATIONS INFORMATION INTEGRATED CIRCUITS FOR CURRENT-SOURCING APPLICATIONS FLOATING LOGIC-GROUND LEVEL Sink D river D w g. No. A 11.532 During recent years, the appearance of many new low-power monolithic devices (LSI and microprocessors) has created an increased


    OCR Scan     		UDN2981A UDN2983A UDN2983/84A reco relay UDN2580A UDN6118A-1 UDN2983 ULN2804A PDF

    74LS189 equivalent

    Abstract: 74LS200 AmZ8036 Z8104 74LS300 AM9511 Am2505 27s13 54S244 27LS00
    Text: Advanced Micro Devices Condensed Catalog 1981 Advanced Micro Devices, Inc. Advanced Micro Devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The company assumes no responsibility for the use of any circuits described herein.


    OCR Scan     		AMD-599 LM101 SN54LS01 132nd 74LS189 equivalent 74LS200 AmZ8036 Z8104 74LS300 AM9511 Am2505 27s13 54S244 27LS00 PDF

    BH1425KN

    Abstract: BH1425KN-1-2 TSZ22111-04 VQFN28 Fm Stereo Transmitter
    Text: PRODUCTS TYPE PAGE Semiconductor 1C BH1425KN 1/4 STRUCTURE Silicon Monolithic Integrated Circuit PRODUCT SERIES Wireless Audio Link LSI for Mobile Phone FM Stereo Transmitter TYPE BH1425KN FEATURE Low voltage Fast Mode l2C-BUS interface. Adjustment free wideband PLL frequency synthesizer (76MHz~ 108MHz).


    OCR Scan     		BH1425KN 76MHz~ 108MHz) TSZ02201 -BH1425KN-1 TSZ22111-04 BH1425KN-1-2 VQFN28 Fm Stereo Transmitter PDF

    ML4008

    Abstract: L64811 l64844 L64852 SparKIT-20 pc motherboard schematics L64801 L64854 L64825
    Text: 5304ÔQ4 001DE53 < ^ 3 « L L C After the SPARCstation from Sun Microsystems became an international workstation standard, vendors began to show increasing interest in the SPARC-compatible market in the United States, along the Pacific rim, and in Europe. To facilitate the design of


    OCR Scan     		001DE53 SPECint92 SPECfp92 SS101 SparKIT-40/Mbus L64831 SparKIT-40/SS2 L64811 IU/L64814 SparKIT-20+ ML4008 l64844 L64852 SparKIT-20 pc motherboard schematics L64801 L64854 L64825 PDF

    BU9428KV

    Abstract: BU9428KV-1 BU9428KV-1-2 TSZ22111-04
    Text: TYPE PRODUCTS SEMICONDUCTOR LSI PAGE B U 9428K V 1/4 Silicon Monolithic integrated circuit USB host MP3 Decoder LSI B U 9428K V Audio products, etc. BU9428KV is MP3 decoder 1C which contains USB host l/F, audio DAC, system controller. •USB2.0 Full Speed host l/F function contained.


    OCR Scan     		BU9428KV BU9428KV TSZ02201-BU9428KV-1 TSZ22111-04 BU9428KV-1 BU9428KV-1-2 PDF

    BU9437AKV

    Abstract: BU9437AKV-1 TSZ22111 SD Card connect USB Host MP3 decoder
    Text: TYPE PRODUCTS PAGE SEM ICONDUCTO R LSI OStructure OProduct name O T yp e OApplications OFunctions BU9437AKV 1/4 Silicon Monolithic integrated circuit USB host W M A+M P3 Decoder LSI BU9437AKV Audio products, etc. BU9437AKV is W M A+M P3 decoder IC which contains USB host and SD card l/F, audio DAC,


    OCR Scan     		BU9437AKV BU9437AKV TSZ02201-BU9437AKV-1 TSZ22111 BU9437AKV-1 SD Card connect USB Host MP3 decoder PDF