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    LOW VOLTAGE CD4027B Search Results

    LOW VOLTAGE CD4027B Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    DF2B5M4ASL Toshiba Electronic Devices & Storage Corporation TVS Diode (ESD Protection Diode), Bidirectional, +/-3.6 V, SOD-962 (SL2) Visit Toshiba Electronic Devices & Storage Corporation
    DF2B6M4ASL Toshiba Electronic Devices & Storage Corporation TVS Diode (ESD Protection Diode), Bidirectional, +/-5.5 V, SOD-962 (SL2) Visit Toshiba Electronic Devices & Storage Corporation
    DF2B5PCT Toshiba Electronic Devices & Storage Corporation TVS Diode (ESD Protection Diode), Bidirectional, +/-3.6 V, SOD-882 (CST2) Visit Toshiba Electronic Devices & Storage Corporation
    DF2B7PCT Toshiba Electronic Devices & Storage Corporation TVS Diode (ESD Protection Diode), Bidirectional, +/-5.5 V, SOD-882 (CST2) Visit Toshiba Electronic Devices & Storage Corporation
    TPD4207F Toshiba Electronic Devices & Storage Corporation Intelligent power device 600V (High voltage PWM DC brushless motor driver) Visit Toshiba Electronic Devices & Storage Corporation

    LOW VOLTAGE CD4027B Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    FT 4013 d dual flip flop

    Abstract: FT 4013 D flip flop 74HC octal bidirectional latch 74HCT 4013 DATASHEET 4511 pin configuration SN7432 fairchild CMOS TTL Logic Family Specifications 7805 acv Datasheet of decade counter CD 4017 sn74154
    Text: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX


    Original     		PDF

    T flip flop IC

    Abstract: pin designation for CD40110B IC 74LS series logic gates 3 input or gate FT 4013 d dual flip flop ic cmos 4011 CD4001* using NAND gates IC CD 4033 pin configuration Quad 2 input nand gate cd 4093 FT 4013 D flip flop 74HCT 4013 DATASHEET
    Text: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX


    Original     		PDF

    5958

    Abstract: 74LS AN-90 C1995 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMJ J16A
    Text: CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset General Description Features These dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and Pchannel enhancement mode transistors Each flip-flop has


    Original     		PDF CD4027BM CD4027BC 5958 74LS AN-90 C1995 CD4027B CD4027BCJ CD4027BMJ J16A

    CD4013B

    Abstract: CD4027BMS IOH15
    Text: CD4027BMS CMOS Dual J-K Master-Slave Flip-Flop December 1992 Features Pinout • High Voltage Type 20V Rating CD4027BMS TOP VIEW • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low”


    Original     		PDF CD4027BMS 16MHz 100nA CD4013B CD4027BMS IOH15

    CD4013B

    Abstract: CD4027BMS IOH15
    Text: CD4027BMS S E M I C O N D U C T O R CMOS Dual J-K Master-Slave Flip-Flop December 1992 Features Pinout • High Voltage Type 20V Rating CD4027BMS TOP VIEW • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low”


    Original     		PDF CD4027BMS 16MHz 100nA CD4013B CD4027BMS IOH15

    CD4027BCM

    Abstract: 74LS AN-90 CD4027BC CD4027BCN M16A MS-001 N16E
    Text: Revised January 2004 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description Features The CD4027BC dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. Each


    Original     		PDF CD4027BC CD4027BC CD4027BCM 74LS AN-90 CD4027BCN M16A MS-001 N16E

    CD4013B

    Abstract: CD4027BMS IOH15
    Text: CD4027BMS CMOS Dual J-K Master-Slave Flip-Flop December 1992 Features Pinout • High Voltage Type 20V Rating CD4027BMS TOP VIEW • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low”


    Original     		PDF CD4027BMS 16MHz 100nA CD4013B CD4027BMS IOH15

    CD4027B

    Abstract: 74LS AN-90 CD4027BC CD4027BCM CD4027BCN M16A MS-001 N16E
    Text: Revised March 2002 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description Features The CD4027BC dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. Each


    Original     		PDF CD4027BC CD4027BC CD4027B 74LS AN-90 CD4027BCM CD4027BCN M16A MS-001 N16E

    N16E

    Abstract: 74LS AN-90 CD4027BC CD4027BCM CD4027BCN M16A MS-001
    Text: Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors. Each


    Original     		PDF CD4027BC CD4027BC N16E 74LS AN-90 CD4027BCM CD4027BCN M16A MS-001

    cd4027b

    Abstract: D4013 SB 125 024 CD4027BF3A real time application of D flip-flop
    Text: Data sheet acquired from Harris Semiconductor SCHS032C − Revised October 2003 The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic packages F3A suffix , 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and


    Original     		PDF SCHS032C CD4027B 16-lead 17-Oct-2005 CD4027BE CD4027BEE4 CD4027BF D4013 SB 125 024 CD4027BF3A real time application of D flip-flop

    master slave jk flip flop

    Abstract: ECL D flip flop Flip Flop DIP Flip flop JK cmos 74lvt16374 d flip flop d type flip flop flip flop flip flop circuit flip flop circuit type D
    Text: Logic Products by Function Flip-Flop Products Logic Product Family Product Description Package Voltage Node 74ACT109 FACT ACT Dual JK Positive Edge-Triggered Flip-Flop DIP SOIC TSSOP 5 DM74LS73A Bipolar-LS Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary


    Original     		PDF 74ACT109 DM74LS73A MM74C73 74AC74 74ACT74 74ACTQ74 16-Bit 74VCXH162374 SCAN182374A master slave jk flip flop ECL D flip flop Flip Flop DIP Flip flop JK cmos 74lvt16374 d flip flop d type flip flop flip flop flip flop circuit flip flop circuit type D

    74LS

    Abstract: AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A
    Text: & February 1988 Semiconductor CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset Features • Wide supply voltage range ■ High noise immunity ■ Low power TTL compatibility ■ Low power ■ Medium speed operation 3.0V to 15V 0.45 VDD typ.


    OCR Scan     		PDF CD4027BM/CD4027BC 74LS AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A

    74LS

    Abstract: AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A CD4027BCN
    Text: & February 1988 Semiconductor CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset Features • Wide supply voltage range ■ High noise immunity ■ Low power TTL compatibility ■ Low power ■ Medium speed operation 3.0V to 15V 0.45 VDD typ.


    OCR Scan     		PDF CD4027BM/CD4027BC 74LS AN-90 CD4027B CD4027BC CD4027BCJ CD4027BM CD4027BMN J16A CD4027BCN

    design of the IC CD4013

    Abstract: cd40138 cd4013 diagram cd4013 CD4013 internal diagram CD4013 IC
    Text: H A R R IS S E M I C O N D U C T O R CD4027BMS CMOS Dual J-K Master-Slave Flip-Flop December 1992 Features • Pinout CD4027BMS TOP VIEW High Voltage Type 20V Rating • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either "High” or "Low”


    OCR Scan     		PDF CD4027BMS CD4027BMS 16MHz 100nA design of the IC CD4013 cd40138 cd4013 diagram cd4013 CD4013 internal diagram CD4013 IC

    Untitled

    Abstract: No abstract text available
    Text: February 1988 CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description Features These dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N- and Pchannel enhancement mode transistors. Each flip-flop has


    OCR Scan     		PDF CD4027BM/CD4027BC

    4027bc

    Abstract: No abstract text available
    Text: CD4027BM/CD4027BC g g National Semiconductor CD4027BM/CD4027BC Dual J-K Master/Slave Rip-Rop with Set and Reset General Description Features These dual J-K flip-flops are monolithic complementary MOS CMOS integrated circuits constructed with N-and P-channet enhancement mode transistors. Each flip-flop


    OCR Scan     		PDF CD4027BM/CD4027BC CD4027BM/CD4027BC 4027bc

    Untitled

    Abstract: No abstract text available
    Text: H A R R IS X Semiconductor CD4027BMS CMOS Dual J-K Master-Slave Flip-Flop December 1992 Pinout Features CD4027BMS • High Voltage Type 20V Rating TOP VIEW • Set - Reset Capability -u • Static Flip-Flop Operation - Retains State Indefinitely


    OCR Scan     		PDF CD4027BMS 16MHz

    CD4013

    Abstract: F3302 harris CD4013B
    Text: f f l U U H A R R CD4027BMS I S S E M I C O N D U C T O R CMOS Dual J-K Master-Slave Flip-Flop Decem ber 1992 Pinout Features C04027BMS TOP VIEW • H ig h V o lta g e T y p e 20V R a tin g • Set - Reset Capability • Static Flip-Flop Operation - Retains State Indefinitely


    OCR Scan     		PDF CD4027BMS C04027BMS 16MHz 100nA CD4013 F3302 harris CD4013B

    cd4027b

    Abstract: No abstract text available
    Text: ^ Tex a s In s t r u m e n t s CD4027B Types Data sheet acquired from Harris S em iconductor S C H S 032 CMOS Dual J-K Master-Slave Flip-Flop High-Voltage Types 20-V o lt Rating • CD4027B is a single monolithic chip integrated circuit containing tw o iden­


    OCR Scan     		PDF CD4027B

    u114

    Abstract: 74LS AN-90 CD4027BC CD4027BCM CD4027BCN M16A MS-001 N16E
    Text: O ctober 1987 Revised January 1999 S E M IC O N D U C T O R T M CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description T he C D 4027BC dual J-K flip-flops are m onolithic com ple­ m entary MOS CM OS integrated circuits constructed with


    OCR Scan     		PDF CD4027BC CD4027BC u114 74LS AN-90 CD4027BCM CD4027BCN M16A MS-001 N16E

    I8082

    Abstract: CD4027B
    Text: iT ! H A R R IS CMOS Dual J-K Master-Slave Flip-Flop High-Voltage Types 2 0 -V o lt Rating • CD4027B is a single m o n o lith ic chip integrated c irc u it containing tw o iden­ tical com plem entary-sym m etry J-K masterslave flip-flo ps. Each flip -flo p has provi­


    OCR Scan     		PDF CD4027B RCA-CD4013B 92CS-2T5SJ I8082

    JT40W

    Abstract: CD4027B
    Text: Z 537T CD4027B Types CMOS Dual J-K Master-Slave Flip-Flop High-Voltage Types {20-V o lt Rating The RCA-CD4027B is a single m onolithic chip integrated circuit containing tw o iden­ tical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provi­


    OCR Scan     		PDF CD4027B RCA-CD4027B RCA-CD4013B 13--Dynamic JT40W

    rs flip-flop IC 7400

    Abstract: RCA-CD4027B 37SdB CD4027B
    Text: T " ^ Ö L j 5"sT/m ^nT ? É J ll3 ? 7 S D ? b D D E M D 7 S ^ f ^ 01E 24072 3875081 G E SOLID STATE T - V é - 01-01 CD4027B Types CMOS Dual J-K Master-Slave Flip-Flop High-Voltage Types 20-Volt Rating The RCA-CD4027B is a single m onolithic chip integrated circuit containing tw o iden­


    OCR Scan     		PDF CD4027B 20-Volt RCA-CD4027B RCA-CD4013B 2CS-21H 13--Dynamic rs flip-flop IC 7400 37SdB

    CD4027B

    Abstract: ty60 RCA-CD4013B 15-V 10de8
    Text: HAR R I S SEMI COND S E C T OR 4ME D • 4 3 0 2 2 7 1 Q 0 3 7 3 R S fl B I H A S — V ^ -0 7 '0 7 HARRIS CMOS Dual J-K Master-Slave Flip-Flop High-Voltage Types {2 0-V o lt Rating ■ CD4027B is a single monolithic chip integrated circuit containing two ¡den*


    OCR Scan     		PDF 43G2271 CD4027B 20-Volt RCA-CD4013B ty60 15-V 10de8