LMQB Search Results

54F676DM

Abstract: 54F676FM 54F676SDM 74F676 74F676PC 74F676SC 74F676SPC N24A N24C
Contextual Info: 54F 74F676 16-Bit Serial Parallel-In Serial-Out Shift Register General Description Features The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode M input is HIGH information present on the parallel

National AN-64

Abstract: 54F544LM 54F544SDM 74F544 74F544MSA 74F544SC 74F544SPC N24C 54F544DM 54F544FM
Contextual Info: 54F 74F544 Octal Registered Transceiver General Description Features The ’F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of

AM248

Abstract: 54F825FM 54F825LM 54F825SDM 74F825 74F825SC 74F825SPC J24F M24B N24C
Contextual Info: 54F 74F825 8-Bit D-Type Flip-Flop General Description Features The ’F825 is an 8-bit buffered register It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems Also included in the ’F825 are multiple enables that allow multiuser control of the interface

9548

Abstract: 54F533DM 54F533FM 54F533LM 74F533 74F533PC 74F533SC 74F533SJ F373
Contextual Info: 54F 74F533 Octal Transparent Latch with TRI-STATE Outputs General Description Features The ’F533 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear transparent to the data when Latch Enable LE is HIGH

74F14 national

Abstract: 54F14DM 54F14FM 54F14LM 74F14 74F14PC 74F14SC 74F14SJ J14A M14A
Contextual Info: 54F 74F14 Hex Inverter Schmitt Trigger General Description The ’F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels They are capable of transforming slowly changing input signals into sharply defined jitter-free output signals In addition they have a greater noise margin than conventional

54F280DM

Abstract: 54F280FM 54F280LM 74F280 74F280PC 74F280SC 74F280SJ F280 J14A N14A
Contextual Info: 54F 74F280 9-Bit Parity Generator Checker General Description Features The ’F280 is a high-speed parity generator checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH If an even number of inputs is HIGH the Sum Even output is HIGH If an odd

INTEL 24 PIN CERAMIC DUAL-IN-LINE PACKAGE

Abstract: 74F545 54F545DM 54F545FM 54F545LM 74F545PC 74F545SC 74F545SJ F545 J20A
Contextual Info: 54F 74F545 Octal Bidirectional Transceiver with TRI-STATE Outputs General Description Features The ’F545 is an 8-bit TRI-STATE high-speed transceiver It provides bidirectional drive for bus-oriented microprocessor and digital communications systems Straight through bidirectional transceivers are featured with 24 mA 20 mA Mil

74F541

Abstract: F540 54F540DM 74F540 74F540PC 74F540SC F240 F244 F541 F54011
Contextual Info: 54F 74F540  54F 74F541 Octal Buffer Line Driver with TRI-STATE Outputs General Description Features The ’F540 and ’F541 are similar in function to the ’F240 and ’F244 respectively except that the inputs and outputs are on opposite sides of the package see Connection Diagrams This pinout arrangement makes these devices especially useful as output ports for microprocessors allowing

74F158APC

Abstract: 54F158ADM 54F158AFM 54F158ALM 74F158A 74F158ASC 74F158ASJ J16A N16E
Contextual Info: 54F 74F158A Quad 2-Input Multiplexer General Description Features The ’F158A is a high speed quad 2-input multiplexer It selects four bits of data from two sources using the common Select and Enable inputs The four outputs present the selected data in the inverted form The ’F158A can also generate any four of the 16 different functions of two variables

54F398DM

Abstract: 54F398FM 54F398LM 74F398 74F398PC 74F398SC 74F399
Contextual Info: 54F 74F398  54F 74F399 Quad 2-Port Register General Description Features The ’F398 and ’F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flipflops A common Select input determines which of the two 4-bit words is accepted The selected data enters the flipflops on the rising edge of the clock The ’F399 is the 16-pin

Contextual Info: 54F243,74F243 54F243 74F243 Quad Bus Transceiver with TRI-STATE Outputs Literature Number: SNOS176A 54F 74F243 Quad Bus Transceiver with TRI-STATE Outputs General Description Features The ’F243 is a quad bus transmitter receiver designed for 4-line asynchronous 2-way data communications between

74f04 texas instruments

Contextual Info: 54F04,74F04 Hex Inverter Literature Number: SNOS146A General Description Features This device contains six independent gates, each of which performs the logic INVERT function. n Guaranteed 4000V minimum ESD protection Ordering Code: See Section 0 Military

Contextual Info: 54F157A,74F157A 54F157A 74F157A Quad 2-Input Multiplexer Literature Number: SNOS155A 54F 74F157A Quad 2-Input Multiplexer General Description Features The ’F157A is a high-speed quad 2-input multiplexer Four bits of data from two sources can be selected using the

74f245

Abstract: 74F245 TEXAS 54F245DM
Contextual Info: 54F245,74F245 54F245 74F245 Octal Bidirectional Transceiver with TRI-STATE Outputs Literature Number: SNOS177A 54F 74F245 Octal Bidirectional Transceiver with TRI-STATE Outputs General Description Features The ’F245 contains eight non-inverting bidirectional buffers

ti 74f14

Abstract: 74f14sc 74F14 national
Contextual Info: 54F14 54F14 Hex Inverter Schmitt Trigger Literature Number: SNOS153A 54F 74F14 Hex Inverter Schmitt Trigger General Description The ’F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels They are capable of transforming slowly changing input signals into sharply defined jitter-free output signals In addition they have a greater noise margin than conventional

54F174DM

Abstract: 54F174FM 54F174LM 74F174 74F174PC 74F174SC 74F174SJ J16A N16E f174
Contextual Info: 54F 74F174 Hex D Flip-Flop with Master Reset General Description Features The ’F174 is a high-speed hex D flip-flop The device is used primarily as a 6-bit edge-triggered storage register The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition The device has a

MD20D

Abstract: F299 54F299DM 54F299FM 54F299LM 74F299 74F299PC 74F299SC 74F299SJ J20A
Contextual Info: 54F 74F299 Octal Universal Shift Storage Register with Common Parallel I O Pins General Description Features The ’F299 is an 8-bit universal shift storage register with TRI-STATE outputs Four modes of operation are possible hold store shift left shift right and load data The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins Additional outputs

74f132 national

Abstract: 54F132DM 54F132FM 54F132LM 74F132PC F132 J14A M14A M14D N14A
Contextual Info: General Description The ’F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In

TC5065

Abstract: 54F191DM 54F191FM 54F191LM 74F191 74F191PC 74F191SC 74F191SJ F191 J16A
Contextual Info: 54F 74F191 Up Down Binary Counter with Preset and Ripple Clock General Description Features The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting The preset feature allows the ’F191 to be used in programmable dividers The Count Enable input the Terminal Count

Contextual Info: December 1994 54F/74F32 Quad 2-Input O R Gate General Description Features This device contains four independent gates, each of which performs the logic OR function. • Guaranteed 4000V minimum ESD protection Military Package Number N14A 14-Lead 0.300" Wide Molded DuaHn-Line

54F657FM

Abstract: 54F657LM 54F657SDM 74F657 74F657SPC 75F657SC F245 F657 N24C
Contextual Info: 54F 74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator Checker and TRI-STATE Outputs General Description Features The ’F657 contains eight non-inverting buffers with TRI-STATE outputs and an 8-bit parity generator checker It is intended for bus-oriented applications The buffers have

74F04SC

Abstract: CERAMIC LEADLESS CHIP CARRIER fmqb 54F04FM 54F04LM 74F04 74F04PC 74F04SJ J14A M14A
Contextual Info: 74F04 Hex Inverter General Description Features This device contains six independent gates, each of which performs the logic INVERT function. n Guaranteed 4000V minimum ESD protection Ordering Code: Commercial Military Package Package Description Number 74F04PC

74F574

Abstract: 54F574DM 54F574FM 54F574LM 74F574PC 74F574SC 74F574SJ F374
Contextual Info: 74F574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The ’F574 is a high-speed, low power octal flip-flop with a buffered common Clock CP and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP)

74F253

Abstract: 54F253DM 54F253FM 54F253LL 74F253PC 74F253SC 74F253SJ F253 J16A N16E
Contextual Info: 74F253 Dual 4-Input Multiplexer with 3-STATE Outputs General Description Features The ’F253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data from four sources using common select inputs. The output may be individually switched to a high impedance state with a HIGH on the respective Output Enable OE inputs, allowing the outputs to