LIFO STACK 16 BIT Search Results

lifo stack 16 bit

Abstract: CFS1020B
Contextual Info: CFS1020B CFS1020B LIFO GENERAL D ESC R IPTIO N : 5 X 16 LIFO CFS1020B is a 16-bit wide last-in-first-out circuit which can be used as a stack with built-in stack pointer. The data is allowed to be written onto the top of the stack during the next clock cycle following

lifo stack

Abstract: AM2932DMB lifo AM2932DC AM2932DM D-20 AM2932
Contextual Info: Am2932 Program Control Unit/Push-Pop Stack DISTINCTIVE CHARACTIERISTICS GENERAL DESCRIPTION • Powerful, 4-bit slice address controller fo r memories Useful w ith both main memory and microprogram memory Expandable to generate any address length • Executes 16 instructions

lifo stack

Abstract: ScansUX1003
Contextual Info: 4708/4708B MICROPROGRAM SEQUENCER FAIRCHILD CMOS M A C R O LO G IC DESCRIPTION - The 4708 Microprogram Sequencer controls the order in which microinstructions are fetched from the control m em ­ ory. It contains a 10-bit program counter, a 4-level last-in first-out

Contextual Info: Am2932 Am2932 Program Control Unit/Push-Pop Stack DISTINCTIVE CHARACTERISTICS Powerful, 4-bit sNce address controller for memories Eight relative address instructions Useful with both main memory and microprogram mem­ ory Expandable to generate any address length

full adder circuit using 2*1 multiplexer

Abstract: 4 bit binary pipeline ripple carry adder full adder using Multiplexer block diagram Am2901s AM2930DC AM2930 AM2930DM AM2930FM pin diagram of full adder using Multiplexer IC AM2930DMB
Contextual Info: Am2930 Program Control Unit DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION • Powerful, 4-bit slice address controller for memories Useful w ith both main memory and microprogram memory Expandable to generate any address length Executes 32 instructions Autom atic generation of address and update of program

lifo stack

Abstract: idm2901 idm2910
Contextual Info: IDM291OA 2900 Family/ Bipolar Microprocessor National Semiconductor PRELIMINARY IDM291 OA Microprogram Controller General Description Features and Benefits The IDM2910A Microprogram Controller is a 12-bit wide address controller packaged in a standard 40-pin dual-in-line package. The IDM2910A features

lifo stack

Abstract: 9408 LIFO BA535 Bmw i3 bmw logic 7 9408 diode ScansUX1004
Contextual Info: 9408 MICROPROGRAM SEQUENCER F A IR C H IL D l3L M A C R O L O G IC D E S C R IP T IO N — The 9 4 0 8 M icro pro gra m S equencer con trols the order in w h ic h m ic ro in s tru c tio n s are fetched fro m the con trol m e m ­ ory. It contains a 1 0 -bit program counter, a 4 -le vel la st-in firs t-o u t

csb 400 P

Abstract: LIFO WD1510 WD1510-00 WD1510-01 WD1510-02
Contextual Info: LIFO/FIFO Buffer Register WD1510-00,-01,-02 FEATURES • Word length selectable: 128 or 132 • 9 bit word width • DC to 650 KHz -00 , 1 MHz (-01), l j MHz (-02) • Empty and full flags • Three-state data lines • 5-volt only • No external clocks required

csb 400 P

Abstract: WD1510 WD1510-00 WD1510-01 WD1510-02
Contextual Info: LIFO/FIFO Buffer Register WD1510-00,-01,-02 FEATURES • Word length selectable: 128 or 132 • 9 bit word width • DC to 650 KHz -00 , 1 MHz (-01), l j MHz (-02) • Empty and full flags • Three-state data lines • 5-volt only • No external clocks required

fairchild 9407

Abstract: fairchild 9423 ci 9410 4703B 4706B F464-2 F464-3 F464-4 16x4-Bit 16x4 fifo
Contextual Info: FAIRCHILD MEMORY SERIAL MEMORY Logic/Connection Diagram 3348 Static Shift Register 1.0 150 C 24 M36 7M 2 32x6 3349 Static S hift Register 1.0 150 C 16 M37 6Z,8K,9B 3 64x4 3341 FIFO 0.7 450/625'» C,L,M 16 M38 6Z,8K 4 64x4 3341A FIFO 1.0 450 C 16 M38 62,8K

ST6210B6

Abstract: ST62E15F6 ST6210 ST62E10F6 2764 eprom ST6215B6 st62xx st60xx PDIP-20 ST6215
Contextual Info: 30E D • 7^537 OOSlbafl 0 ■ r S G S -T H O M S O N -\°\-08 ST6210/E10 ST6215/E15 8 BIT HCMOS MICROCONTROLLERS WITH A/D CONVERTER S G S-TH0MS0N ;_ P R E L IM IN A R Y D A T A ■ 8-BIT ARCHITECTURE ■ HCMOS LOW POWER CONSUMPTION ■ SINGLE POWER SUPPLY - 3.0V TO 6.0V

pin diagram of full adder using Multiplexer IC

Abstract: 4 bit binary pipeline ripple carry adder 5252 F ic full adder circuit using 2*1 multiplexer AM2930 32 bit ripple carry adder AM2930DC
Contextual Info: Am2930 Am2930 Program Control Unit DISTINCTIVE CHARACTERISTICS Powerful, 4-bit slice address controller lor memories Useful with both main m em ory and m icroprogram m em ­ ory E xpandable to g e n era te any address length Executes 32 instructions Capable of executing branch and subroutine call

pin diagram of full adder using Multiplexer IC

Abstract: 5252 F ic full adder circuit using 2*1 multiplexer AM2930 pin diagram of full adder using Multiplexer IC 74 4 bit binary pipeline ripple carry adder
Contextual Info: Am2930 Am2930 Program Control Unit DISTINCTIVE CHARACTERISTICS Powerful, 4-bit slice address con troller lo r m em ories U s e fu l w ith b o th m a in m e m o ry a n d m ic ro p ro g ra m m e m ­ ory E x p a n d a b le to g e n e ra te a n y a d d re s s le n g th

4702B

Abstract: 4703B 4704B 4705B 4706B 4707B 4708B 4710B F464-2 F464-3
Contextual Info: FAIRCHILD MEMORY SERIAL MEMORY Logic/Connection Diagram 3348 Static Shift Register 1.0 150 C 24 M36 7M 2 32x6 3349 Static S hift Register 1.0 150 C 16 M37 6Z,8K,9B 3 64x4 3341 FIFO 0.7 450/625'» C,L,M 16 M38 6Z,8K 4 64x4 3341A FIFO 1.0 450 C 16 M38 62,8K

68300-series

Abstract: motorola 68020 instruction set 68EC000 68HC16 MCF5307 68060 lifo Tricore Hitachi DSA00357 motorola 68060
Contextual Info: MICROPROCESSOR T H E I N S I D E R S ’ G U I D E T O M I C R O P R O C E S S O R VOLUME 12, NUMBER 14 OCTOBER 26, 1998 REPORT H A R D W A R E ColdFire Doubles Performance With v4 Changes to Core Design, Clock Speed Accelerate Motorola’s Midrange CPU Version 4 Adds New Instructions

16x4-Bit

Abstract: 4702B 4703B 4704B 4705B 4706B 4707B 4708B 4710B F464-2
Contextual Info: FAIRCHILD MEMORY SERIAL MEMORY Logic/Connection Diagram 3348 Static Shift Register 1.0 150 C 24 M36 7M 2 32x6 3349 Static S hift Register 1.0 150 C 16 M37 6Z,8K,9B 3 64x4 3341 FIFO 0.7 450/625'» C,L,M 16 M38 6Z,8K 4 64x4 3341A FIFO 1.0 450 C 16 M38 62,8K

Goldstar TV 23

Contextual Info: GOLDSTAR TECHNOLOGY 4028757 GOLDSTAR TECHNOLOGY INC-, D4E D | 4D2fl757 □□□lfifl3 fl INC. 04E 01883 D GD4708B/GD4708BX MICROPROGRAM SEQUENCER DESCRIPTION — The 4708B/4708BX Microprogram Sequen­ cer controls the order in which microinstructions are fetched

idt39c10

Contextual Info: Integrated Device Technology, Inc. 12-BIT CMOS MICROPROGRAM SEQUENCER FEATURES: • microprogram sequencers are intended for use in controlling th e se q u e n ce of m ic ro in s tru c tio n s e xe cu te d in the microprogram memory. The IDT39C10s provide several

lifo stack

Abstract: pin diagram of full adder using Multiplexer IC pinout AM2 AMD D-20 20-PIN CERDIP 4560d
Contextual Info: Am2932 Am 2932 Program Control Unit/Push-Pop Stack DISTINCTIVE CHARACTERISTICS Eight relative address instructions Including Jum p relative and Jum p-to-Subroutine rela­ tive S eventeen-level pu sh /po p stack On-chip storage o f subroutine return addresses

Contextual Info: 12-BIT CM O S MICROPROGRAM SEQ UENCER IDT39C10B id t 39C10C Inreg^red D evice Technology Jnc MICROSLICE PRODUCT FEATURES: DESCRIPTION: • Low-power CEMOS ™ The IDT39C10 microprogram sequencers are designed for use in high-performance microprogram state machines. These micro­

IDT39C10

Abstract: pc 2581 v micro pc 2581 IDT39C10B lifo stack S1QB
Contextual Info: INTEGRATE] DEVICE SflE D 12-BIT CMOS MICROPROGRAM SEQUENCER • 4BES771 DDlOflBZ 735 ■ IDT IDT39C10B IDT39C10C ■ 4 ct - l 7 - S \ microprogram sequencers are intended for use in controlling the sequence of m icroinstructions executed in the microprogram memory. The IDT39C10s provide several

amd am2 pinout

Abstract: FPLR cable pin diagram of full adder using Multiplexer IC FPLR pinout AM2 AMD AM2932 D-20 4560d 20-PIN CERDIP i3081
Contextual Info: Am2932 Am 2932 Program Control Unit/Push-Pop Stack DISTINCTIVE CHARACTERISTICS Eight relative address instructions Including Jum p relative and Jum p-to-Subroutine rela­ tive S eventeen-level pu sh /po p stack On-chip storage o f subroutine return addresses

lifo

Contextual Info: STANDARD MICROSYSTEMS SR 5017 SR 5018 mrmrmnri Quad Static Shift Right/Shift Left Shift Register Last In First Out Buffer LIFO FEATURES □ COMPLAMOS N-Channel Silicon Gate Technology. □ Quad 81 bit or Quad 133 bit □ Directly Compatible with T2L, MOS

Contextual Info: Integrated Device Technology, Inc. 12-BIT CMOS MICROPROGRAM SEQUENCER FEATURES: • Low-power CMOS — Icc max. Military: 90mA Commercial: 75mA • Fast — IDT39C10B matches 2910A speeds — IDT39C10C 30% speed upgrade • 33-Deep stack — Accom modates highly nested loops and subroutines