L2 CACHE CONTROLLER MIPS Search Results

mii to hdlc

Abstract: MPC8540 MPC8541E MPC8555E MPC8560 e500 dhrystone
Contextual Info: Integrated Communications Processors MPC8560/E PowerQUICC III Processor Overview MPC8560 Block Diagram The PowerQUICC™ III is a versatile integrated communications processor designed for a variety of compute-intensive applications, 256 KB L2 Cache I2C Controller

vrc5476

Abstract: VR12000 VR7701 VRC5074 VR4181 NEC VR10000 "embedded dram" nec MIPS64 VR4121 vrc4375
Contextual Info: VR7701 VR Series 64-Bit MIPS RISC Microprocessor Description The 64-bit VR7701 µPD30771 MIPS® microprocessor is particularly suited for designs requiring a high-performance embedded system processor. Features include a 133 MHz double data rate (DDR) SDRAM controller, 133 MHz PCI-X interface, an on-chip L2 cache,

diac kr 206

Abstract: LT 8521 ND4700 ND4700-BRG LT 5219
Contextual Info: Big Dipper R4400/R4600/R4700 PCI Bus Bridge ND4700-BRG Chapter 1. Overview Cache tag SRAM Interface ND4700-BRG Big Dipper is a CPU local bus and PCI bus controller chip designed for use with MIPS Cache & tag SRAM test Interface R4400/R4600/R4700. Its main function is as follows.

Marvell

Abstract: MIPS64 RM-90 RM9000x2 Integrated Multiprocessor E9000
Contextual Info: RM9000x1 Preliminary RM9000x1 Integrated Microprocessor FEATURES E9000 CPU CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9000x1 Integrated Processor is a high performance 64-bit MIPS -based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the

Marvell

Abstract: MIPS64 RM9100A RM9200A 64120A 64-ENTRY
Contextual Info: RM9100A Released Integrated Microprocessor FEATURES E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A

Contextual Info: RM9100A Released AM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A

marvell ethernet switch

Abstract: Marvell MIPS64
Contextual Info: RM9100 Released RM9100 Integrated Microprocessor FEATURES E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100 Integrated Processor is a high performance 64-bit MIPS -based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9100™

RM9200

Abstract: hypertransport Marvell MIPS64
Contextual Info: RM9100 Released RM9100 Integrated Microprocessor FEATURES E9000 CORE PMC-Sierra’s RM9100 Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200 Integrated Multiprocessor.

FLOATING POINT Co Processor

Contextual Info: RM9100A Released PM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A

Marvell

Abstract: MIPS64 RM9100A RM9200A
Contextual Info: RM9100A Released AM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A

Contextual Info: RM9100A Released PM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A

Contextual Info: RM9224 Preliminary RM9224 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9224 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:

RM9224

Abstract: DDR PHY ASIC MIPS64 "network interface cards" 896-pin pmc
Contextual Info: RM9224 Released RM9224 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9224 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:

DDR PHY ASIC

Abstract: MIPS64 RM9220
Contextual Info: RM9220 Released Integrated Multiprocessor FEATURES The RM9220 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:

ddr ram

Contextual Info: RM9222 Preliminary RM9222 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9222 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:

corelis controller

Abstract: MIPS64 ethernet mac
Contextual Info: RM9222 Released RM9222 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9222 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:

DDR PHY ASIC

Abstract: MIPS64 RM9000x2
Contextual Info: RM9222 RM9000x2GL Preliminary RM9222 RM9000x2GL Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9222 RM9000x2GL Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPSbased RM9000 Family processors by providing features specifically suited for

Contextual Info: BCM1455 QUAD-CORE 64-BIT MIPS® PROCESSOR FEATURES SUMMARY OF BENEFITS 64-bit MIPS® CPUs, scalable from 800 MHz–1.2 GHz • •Four Quad-issue in-order pipeline with dual-execute and dual- • • • • • • • performance • Industry-leading

BCM1250

Abstract: BCM1255 BCM1280 BCM1455 BCM1480 BCM5690 BCM5823 MIPS64 higig protocol overview memory bandwidth
Contextual Info: BCM1455 QUAD-CORE 64-BIT MIPS® PROCESSOR NEW! FEATURES SUMMARY OF BENEFITS 64-bit MIPS® CPUs, scalable from 800 MHz–1.2 GHz • •Four Quad-issue in-order pipeline with dual-execute and dual- • • • • • • • performance • Industry-leading

BCM1250

Abstract: BCM1255 BCM1280 BCM1455 BCM5841 MIPS64 memory bandwidth
Contextual Info: BCM1255 DUAL-CORE 64-BIT MIPS® PROCESSOR NEW! SUMMARY OF BENEFITS FEATURES • Two 64-bit MIPS® CPUs, scalable from 800 MHz–1.2 GHz • • • • • • • • Quad issue in-order pipeline with dual-execute and dual-memory pipes • Enhanced skew pipeline enables a zero load-to-use penalty

Contextual Info: BCM1280 DUAL-CORE 64-BIT MIPS® PROCESSOR WITH SPI-4/HT FEATURES • Two 64-bit MIPS® CPUs, scalable from 800 MHz–1.2 GHz • • • • • • • • • • Quad issue in-order pipeline with dual-execute and dualmemory pipes • Enhanced skew pipeline enables a zero load-to-use penalty

broadcom gps

Abstract: BCM1250 BCM1255 BCM1280 BCM1455 BCM1480 MIPS64
Contextual Info: BCM1280 DUAL-CORE 64-BIT MIPS® PROCESSOR WITH SPI-4/HT NEW! FEATURES • Two 64-bit MIPS® CPUs, scalable from 800 MHz–1.2 GHz • • • • • • • • • • Quad issue in-order pipeline with dual-execute and dualmemory pipes • Enhanced skew pipeline enables a zero load-to-use penalty

BCM1250

Abstract: BCM1255 BCM1280 BCM1455 BCM1480 MIPS64 memory bandwidth ge sb1 broadcom mips
Contextual Info: BCM1480 QUAD-CORE 64-BIT MIPS® PROCESSOR WITH SPI-4/HT NEW! 64-bit MIPS® CPUs, scalable from 800 MHz–1.2 GHz • •Four Quad-issue in-order pipeline with dual-execute and dual- • • • • • • • • • memory pipes • Enhanced skew pipeline enables a zero load-to-use penalty

RM9122

Abstract: MIPS64
Contextual Info: RM9122 Preliminary FEATURES AM RM9122 Integrated Microprocessor NETWORKING INTERFACES • A CPU core compatible with the MIPS64 Instruction Set Architecture. • High-speed integrated DDR SDRAM, Local Bus, PCI, and Ethernet MAC interfaces. Option to bypass the