KS74HCTL Search Results

Contextual Info: SAMSUNG SEMICO ND UCTOR INC 05 KS54HCTLS 0 0 / 1 KS74HCTLS * o u D e | 7*11.4145 000fc.4fl3 D 9-Bit Parity Generators/Checkers FEATURES DESCRIPTION • Generates Odd or Even Parity for Nine Data Lines • Cascadable for N-Bits Parity • Can be used to Upgrade Existing Systems using MSI

samsung nand derating

Contextual Info: KS54HCTLS . . . _ KS54HCTLS . „ _ KS74HCTLS 7 0 7 A KS74HCTLS 163A Synchronous 4-Bit Binary Counters These are synchronous, presettable 4-bit binary counters featuring in­ ternal carry-look-ahead for high-speed counting.'The buffered clock in­ put triggers all flip-flops simultaneously on the rising edge of the input

Contextual Info: 7TL.4142 00DL.4t.fci 0 S A M S U N G S E M I C O N D U C T O R INC 02 KS54HCTLS O M KS74HCTLS " 1 i-of-8 Data Selectors/Multiplexers with 3-State Outputs 7 -0 ? / - s 'f FEATURES DESCRIPTION • Three-State Version of '151 • Three-State Outputs Interlace Directly with System

Contextual Info: KS54HCTLS KS74HCTLS 540 KS54HCTLS KS74HCTLS 541 Octal Buffers and Line Drivers with 3-States Outputs The '5 4 0 and '541 are general purpose high-speed octal line drivers/buf­ fers with 3-state outputs. The inputs and outputs are located on opposite sides of the 20-pin package, thus improving circuit board density. The

HCTLS

Contextual Info: SAMSUNG SE MIC ONDU CT OR INC os de| 7Tb4ma KS54HCTLS H O O KS74HCTLS • DDGtasi 0 63 51 D Quad Schmitt-Trigger NAND Gates Preliminary Specifications FEATURES DESCRIPTION • Function, pin-out, speed and drive compatibility with These Schmitt-trigger d evices contain four Independent

Contextual Info: asag SAMSUNG SEMICONDUCTOR KS54HCTLS - / Q O KS74HCTLS 1 INC OS De| 7 ^ 1 4 2 0Q0t.M3b 1 Synchronous 4-Bit Up/Down Binary Counters with Dual Clock FEATURES DESCRIPTION • Look-ahead circuitry enhances cascaded counters • Fully synchronous In count modes

Contextual Info: SAM SU NG SE MI CONDU CT OR INC OS KS74HCTLS ^ D E | 7T b 4145 B0 0b3 ô5 □ | 3 1 8-Bit Serial-in!Paraliei-0 ut Shift Registers FEATURES DESCRIPTION • AND—Gated enablefdisable serial Inputs » Fully buffered clock and serial Inputs • Direct clear

Samsung 546

Abstract: S74HCTLS
Contextual Info: SAMSUNG S E M I CON DU CT OR INC DE. D e J 7 ^ 4 1 4 2 KS74HCTLS POOhMOS b 4-Bit O-Type Registers with 3-State Outputs Objective Specifications -ö S " FEATURES DESCRIPTION - • Gated output control lines for enabling or disabling the outputs • Fully independent clock for operation in paralleMoad

Contextual Info: SAMSUNG SEMICONDUCTOR KS54HCTLS 1 fZ Q /1 f% Q KS74HCTLS l o o / INC 0 E DeJ 7 ^ 4 1 4 2 OOOl^V Synchronous 4-Bit Up/Down Decade and Binary Counters FEATURES DESCRIPTION • Fully Synchronous Operation for Counting and Pro­ gramming • Internal Look Ahead for Fast Counting

Contextual Info: SAMSUNG SEMICONDUCTOR INC KS54HCTLS - j Q j KS74HCTLS D2 TËJ 7^4142 ODGb42ñ 2 Synchronous 4-Bit Up/Down Binary Counters T ^ r - ^ 3 -0 7 FEATURES DESCRIPTION • Single down/up count control line • Look-ahead circuitry enhances speed of cascaded counters

Hctls05

Contextual Info: S A M S U N G S E M I C O N D U C T O R INC OS KS54HCTLS f ì C KS74HCTLS w De J 7 ^ 4 1 4 2 Q00b5fl4 4 Hex Inverters with Open-Drain Outputs — -:-• — t FEATURES DESCRIPTION • Function, pln-out, speed and drive compatibility with

PRE13

Contextual Info: SAMSUNG SEM ICO ND UC TOR INC 05 KS54HCTLS f i d U f i A d KS74HCTLS O H O / O H H Preliminary Specifications D E ^ 7*31 4 1 4 S OOObbES ^ | 9-Bit Bus Interface D-Type Latches with 3-State Outputs . FEATURES DESCRIPTION • Bus-Structured Pinout : ; • Provide Extra Bus Driving Latches

Contextual Info: _ i SAMSUNG S E M I C O N D U C T O R INC 05 DE J 7 ^ b H m a 0001517 1 | 65 17 D Dual Retriggerable Monostable Multivibrator with Clear T - S '^ / 9 KS54HCTLS A Q O KS74HCTLS Preliminary Specifications FEATURES DESCRIPTION • Simple pulse width formula tw -0 < 45Rc

409 samsung

Contextual Info: KS54HCTLS KS74HCTLS . KS54HCTLS KS74HCTLS 174 175 Hex/Quad D-type Flip-Flops with Clear 16 Dip Unit: mm The '1 7 4 contains six, and the '1 7 5 contains four D-type filp-flops all sharing a common clock and a common clear. The '1 7 4 features single­ rail outputs for every flip-flops whereas the '1 7 5 has complementary

Contextual Info: SAMSUNG SEMICONDUCTOR INC 02 KS54HCTLS I C O KS74HCTLS DE|7Tt.4m2 0D0b3bfl □ J ^ j : Dual 1-of~4 Data Selectors/Multiplexers FEATURES DESCRIPTION • Allows Multiplexing from N Lines to 1 Line • Perforins Parallel-to-Serial Conversion • Strobe Enable Line Provided for Cascading

Contextual Info: 1 S A M S U N G S E M I C O N D U C T O R INC OE D ElTTL^m a 5181519 KS74HCTLS 520/521/522 000t,S23 7 8-Bit Identity Comparators FEATURES DESCRIPTION • Compares two 8-bit words • ’518, ’520 and ’522 have 20KR Pull-up resistors on Q Inputs These identity comparators perform comparisons on two

diode t25 4 d7

Contextual Info: 6365 7 SAMSUNG SEMICONDUCTOR INC 05 KS54HCTLS A C H KS74HCTLS Í U 1 D j . ¿à?/- * / " ~ 1-of-8 Data Selectors/Multiplexers FEATURES DESCRIPTION • Can perform as: Boolean Function Generators Parallel-to-Serial Converters Data Source Selectors • Function, pin-out, speed and drive compatibility with

samsung 649

Abstract: KS74HCT 06A06 BD 649 equivalent
Contextual Info: SAMSUNG SEMICONDUCTOR INC 05 D e | 7Tt4-meMDDDtSps Octal D-Type Flip-Flops with Clock Enable KS54HCTLS KS74HCTLS FEATURES - • Can be used lor Implementing — Buffer/Storage Registers ' / V' — Shift Registers -iP a tte rn G e n e r a to rs .-1 ; • Function, pinout, speed and drive compatibility with

8 bit to bcd

Contextual Info: SAMSUNG SEMICONDUCTOR KS54HCTLS “¡ Q 2 KS74HCTLS INC G2 D e 7 ci b 4 m 2 DDGb432 Synchronous 4-Bit Up/Down Decade Counters with Dual Clock FEATURES DESCRIPTION • Look-ahead circuit enhances cascaded counters • Fully synchronous in count modes • Parallel asynchronous load for modulo-N count

Contextual Info: SAMSUNG S E M I C O N D U C T O R INC 05 7Tt,4mE ODDti3t4S T | Dual Retriggerable Monostable Multivibrator with Clear 7^57 -7 f KS54HCTLS 4 0 0 KS74HCTLS f " Preliminary Specifications FEATURES DESCRIPTION • Simple pulse width formula tw = 0-4!>RC • DC triggered frorp active HIGH or active Low inputs

Contextual Info: SAMSUNG SEMICONDUCTOR INC G2 Synchronous 4-Bit Up/Down Decade Counters KS54HCTLS 1 Q f KS74HCTLS FEATURES DESCRIPTION • Single down/up count control line • Look-ahead circuitry enhances speed of cascaded counters • Fully synchronous In count modes

hctls86

Contextual Info: SAMSUNG SEMICONDUCTOR INC OB DE^ 7 H m M a K S S 4 H C T L S O ^ . KS74HCTLS 000^330 7 '7_" - ^ 3 -v2 Quad 2-Input Exclusive-OR Gates FEATURES DESCRIPTION • Function, pin-out, speed and drive compatibility with 54/74LS logic family

Contextual Info: SAMSUNG S EM IC ON DUCTOR IN C 03' DE • 7 ^ 4 1 4 2 KS54HCTLS KS74HCTLS FEATURES • • • • • < • • ' • • • ■ • OQOb444 0 4-Bit Bidirectional Universal Shift Registers " " DESCRIPTION V Parallel-to-Serial, Serlal-to-Parallel Conversions

semiconductor449

Contextual Info: S A M S U N G ^ S E M I C O N D U C T O R INC OH K S ^ d H fìT I S O T ' D È I 7 U 4 1 4 5 D 0 0 b 3 Q S Û J"" ^ " KS74HCTLS " T " 4 3 'Ä I Triple 3-Input NOR Gates FEATURES DESCRIPTION • Function, pln-out, speed and drive compatibility with S4/74LS logic family