CDC2510A
Abstract: KMM375S3227BT-G0 KMM375S3227BT-G8 KMM375S3227BT-GH KMM375S3227BT-GL d11u D16U
Text: Preliminary KMM375S3227BT SDRAM MODULE KMM375S3227BT SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on Stacked 32Mx4, 4Banks 4K Ref., 3.3V SDRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM375S3227BT is a 32M bit x 72 Synchronous Dynamic RAM high density memory module. The Samsung KMM375S3227BT consists of eighteen CMOS Stacked
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KMM375S3227BT
KMM375S3227BT
32Mx72
32Mx4,
32Mx4
400mil
18-bits
24-pin
CDC2510A
KMM375S3227BT-G0
KMM375S3227BT-G8
KMM375S3227BT-GH
KMM375S3227BT-GL
d11u
D16U
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CDC2510A
Abstract: KMM377S3227BT1-GL MA2180
Text: SDRAM MODULE Preliminary KMM377S3227BT1 Revision History Revision 4 May 1998 - CLK Input Cap. is added by PLL Input Cap. (27pF) Revision 5 (July 1998) - "REGE" description is changed. REV. 5 July 1998 Preliminary KMM377S3227BT1 SDRAM MODULE KMM377S3227BT1 SDRAM DIMM (Intel 1.0 ver. Base)
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KMM377S3227BT1
KMM377S3227BT1
32Mx72
32Mx4,
32Mx4
400mil
18-bits
CDC2510A
KMM377S3227BT1-GL
MA2180
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CDC2509
Abstract: MA2180
Text: SDRAM MODULE Preliminary KMM377S3227BT Revision History Revision .2 Jan. 1998 •DC Characteristics values are changed. : ICC2 N & ICC3 N •STANDARD TIMING DIAGRAM is changed . •All AC parameters are measured by module tap reference(refer to page#5) •CAS Latency is based on Reg. DIMM (In case of Unbuff. DIMM CAS Latency is 1 CLK earlier than this)
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KMM377S3227BT
200mA.
100Min
540Min)
250Max
35Max)
010Max
32Mx4
KM44S32037BT
CDC2509
MA2180
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Untitled
Abstract: No abstract text available
Text: Preliminary KM M375S3227BT SDRAM MODULE KMM375S3227BT SDRAM DIMM 32M x72 SDRAM DIMM with PLL & R egister based on Stacked 32M x4, 4B anks 4K Ref., 3.3V S D R AM s with SPD FEATURE G E N E R A L DESCRIPTION • Performance range The Samsung KMM375S3227BT is a 32M bit x 72 Synchro
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OCR Scan
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KMM375S3227BT
M375S3227BT
400mil
18-bits
24-pin
168-pin
375S3227BT
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1-30N
Abstract: No abstract text available
Text: Preliminary KMM377S3227BT1 SDRAM MODULE KMM377S3227BT1 SDRAM DIMM Intel 1.0 ver. Base 32Mx72 SDRAM DIMM with PLL & Register based on Stacked 32Mx4, 4Banks 4K Ref., 3.3V SDRAMs with SPD GENERAL DESCRIPTION FEATURE The Samsung KMM377S3227BT1 is a 32M bit x 72 Synchro
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OCR Scan
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PDF
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KMM377S3227BT1
KMM377S3227BT1
32Mx72
32Mx4,
32Mx4
400mil
18-bits
24-pin
1-30N
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Untitled
Abstract: No abstract text available
Text: SDRAM MODULE Preliminary KMM377S3227BT1 Revision History Revision 4 May 1998 - CLK input Cap. is added by PLL Input Cap. (27pF) Revision 5 (July 1998) - "REGE" description is changed. REV. 5 July 1998 Preliminary KMM377S3227BT1 SDRAM MODULE KMM377S3227BT1 SDRAM DIMM (Intel 1.0 ver. Base)
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OCR Scan
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PDF
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KMM377S3227BT1
KMM377S3227BT1
377S3227BT1-G8
125MHz
32Mx4
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