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    JK FAIRCHILD Search Results

    JK FAIRCHILD Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    54ABT245/BRA Rochester Electronics LLC Replacement for Fairchild part number 5962-9214801QRA. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy
    74F403SPC Rochester Electronics LLC Replacement for Fairchild part number 74F403SPC. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy
    54F38/QCA Rochester Electronics LLC Replacement for Fairchild part number 54F38/BCA. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy
    93425ADM/B Rochester Electronics LLC Replacement for Fairchild part number 93425ADMQB. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy
    54ABT245/B2A Rochester Electronics LLC Replacement for Fairchild part number 5962-9214801Q2A. Buy from authorized manufacturer Rochester Electronics. Visit Rochester Electronics LLC Buy

    JK FAIRCHILD Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: 54ACT112 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop Literature Number: SNOS434A July 20, 2009 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 'ACT112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state


    Original     		PDF 54ACT112 54ACT112 SNOS434A ACT112

    74F109

    Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
    Text: Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.


    Original     		PDF 74F109 74F109SC 16-Lead MS-012, 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E

    74F109

    Abstract: F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild
    Text: Revised September 2000 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.


    Original     		PDF 74F109 74F109SC 16-Lead MS-012, 74F109 F109 74F109PC 74F109SC 74F109SJ M16A M16D MS-001 N16E 74f109 fairchild

    74AC109SC

    Abstract: 74AC109 74AC109PC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
    Text: Revised October 1998 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to CD Clear sets Q to LOW level The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking


    Original     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109SC 74AC109 74AC109PC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC

    74AC109

    Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
    Text: Revised November 1999 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock


    Original     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC

    74AC109MTC

    Abstract: 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109SC
    Text: Revised August 2000 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock


    Original     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109MTC 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109SC

    74F114

    Abstract: 74F114PC 74F114SC F114 M14A N14A
    Text: 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at


    Original     		PDF 74F114 74F114 74F114PC 74F114SC F114 M14A N14A

    Untitled

    Abstract: No abstract text available
    Text: 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description • ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the


    Original     		PDF 74AC109, 74ACT109 AC/ACT109 AC/ACT74 ACT109 74ACT109

    74AC109

    Abstract: 74AC109MTC 74ACT109 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC
    Text: 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description • ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the


    Original     		PDF 74AC109, 74ACT109 AC/ACT109 AC/ACT74 ACT109 74ACT109 74AC109 74AC109MTC 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC

    74F109

    Abstract: 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E
    Text: Revised January 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to CD sets Q to LOW level The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.


    Original     		PDF 74F109 74F109SC 16-Lead MS-012, 74F109 74F109PC 74F109SC 74F109SJ F109 M16A M16D MS-001 N16E

    74F112

    Abstract: 74F112PC 74F112SC 74F112SJ F112 M16A M16D N16E
    Text: 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly


    Original     		PDF 74F112 74F112 74F112PC 74F112SC 74F112SJ F112 M16A M16D N16E

    74F112

    Abstract: 74F112PC 74F112SC 74F112SJ M16A M16D MS-001 N16E
    Text: Revised September 2000 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not


    Original     		PDF 74F112 74F112 74F112PC 74F112SC 74F112SJ M16A M16D MS-001 N16E

    5962-8995001MFA

    Abstract: 5962-8995001B2A smd SD1
    Text: 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’ACT112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly


    Original     		PDF 54ACT112 ACT112 5962-8995001S2A 5962-8995001SEA 5962-8995001SFA 54ACT112DM-MLS 54ACT112FM-MLS 1-Sep-2000] 5962-8995001MFA 5962-8995001B2A smd SD1

    Untitled

    Abstract: No abstract text available
    Text: 54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop Simultaneous LOW on CD and SD makes both Q and Q General Description The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock


    Original     		PDF 54AC109 54ACT109 ACT109 ACT74 54ACT109FM-MLS AN-925:

    54ACT112

    Abstract: ACT112 J16A
    Text: 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’ACT112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly


    Original     		PDF 54ACT112 ACT112 54ACT112 J16A

    9S109

    Abstract: ScansUX1001
    Text: FAIRCHILD SUPER HIGH SPEED TTL/SSI • 9S109 DUAL JK FLIP-FLOP DESCRIPTION - The 9S109 consists of two high speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins


    OCR Scan     		PDF 9S109 9S109, ScansUX1001

    74H102

    Abstract: 10mAVCC ScansUX995
    Text: FAIRCHILD HIGH SPEED TTL/SSI . 9H102/54H102, 74H102 JK EDGE TRIGGERED FLIP-FLOP WITH AND INPUTS DESCRIPTION — The HSTTL/SSI 9H 102/54102, 74H102 is a High Speed JK Negative Edge Triggered flip-flop. They feature gated JK inputs and an asynchronous clear input. The A N D gate inputs are inhibited while the clock input is LOW; when the clock goes H IG H , the inputs are


    OCR Scan     		PDF 9H102/54H102, 74H102 9H102/54102, 10mAVCC ScansUX995

    9L24

    Abstract: ScansUX997
    Text: LPTTL/SSI 9L24 LOW POWER DUAL JK OR D FLIP-FLOP DESCRIPTIO N — The Low Power TTL/SSI 9L24 consists of two completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins


    OCR Scan     		PDF 16-LEAD 500ns- 9L24 ScansUX997

    74H103

    Abstract: clock schematic ScansUX995 Flip-Flop on off 54H103
    Text: FAIRCHILD HIGH SPEED TTL/SSI • 9H103/54H103, 74H103 DUAL JK EDGE TRIGGERED FLIP-FLOP WITH SEPARATE CLEARS AND CLOCKS DESCRIPTION - The HSTTL/SSI 9H 103/54H 103, 74H 103 is a High Speed JK Negative Edge Triggered flip -flo p . They feature individual J, K,


    OCR Scan     		PDF 9H103/54H103, 74H103 clock schematic ScansUX995 Flip-Flop on off 54H103

    Untitled

    Abstract: No abstract text available
    Text: AC109 • ACT109 54AC/74AC109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of


    OCR Scan     		PDF AC109 ACT109 54AC/74AC109 54ACT/74ACT109 ACT109 ACT74 54/74A

    fairchild micrologic

    Abstract: ML9926 HL9926 Structure of D flip-flop COUNTER MODULO 504 674 V 2N1990 FD600 ic_9926 nixie clock
    Text: 9926 JK FLIP-FLOP ELEMENT TEMPERATURE R A N G E S - 5 5 ° C TO+125°C FULL RANGE 0°C TO +100°C (MID RANGE) FAIRCHILD PLANAR* EPITAXIAL MICROLOGIC INTEGRATED CIRCUITS JK FLIP-FLOP DESCRIPTION T he F a irc h ild JK F lip -F lo p is a co m p lete, g e n e ra l p u rp o se, sto rag e elem ent su itab le fo r u se in


    OCR Scan     		PDF iL9926 iL9926 HL9926 jiL9926 pL9926 2N2368 30VDC 2N1990 110VDC fairchild micrologic ML9926 Structure of D flip-flop COUNTER MODULO 504 674 V FD600 ic_9926 nixie clock

    ACT109

    Abstract: ACT74
    Text: AC109 • ACT109 54AC/74AC109 • 54 ACT/74 ACT 109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of


    OCR Scan     		PDF AC109 ACT109 54AC/74AC109 ACT/74 ACT74 ACT109 54/74AC/ACT

    IC 7476

    Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
    Text: FAIRCHILD TTL/SSI . 9N76/5476, 7476 D UA L JK M A STER /SLA VE F LIP -F LO P W ITH SEPARATE PRESETS, CLEARS A N D CLOCKS DESCRIPTION — The T TL/S SI 9N 76 /54 7 6 , 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks.


    OCR Scan     		PDF 9N76/5476, 11N76/7476 400ft IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476

    74AC109

    Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 M16A M16D
    Text: S H IU D Revised O ctober 1998 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LO W input to Cp Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking


    OCR Scan     		PDF 74AC109 74ACT109 AC/ACT109 AC/ACT74 ACT109 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 M16A M16D