JESD816 Search Results
JESD816 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
---|---|---|---|
ep4cgx30f484
Abstract: EP4CE115 CYIV-5V1-1 EP4CGX EP4CE55 EP4CE15 sigma delta lcd screen lvds 40 pin diagram ep4ce22 ep4ce40
|
Original |
||
EP4CE15
Abstract: F169 Texas Instruments Cyclone IV EP4C Series Power Reference Designs ep4ce40 CYIV-5V1-1 4CGX75 V-by-One n148 TYPE SKP 38 CL 9001 ep4cgx30f484
|
Original |
||
add round key for aes algorithm
Abstract: detail of half adder ic DIN 5463 2-bit half adder handbook texas instruments IC to design 2 by 2 binary multiplier SE 135 pin configuration verilog code for twiddle factor ROM transistor c789 6A ep3sl1501152
|
Original |
||
AIIGX53001-3
Abstract: half bridge converter 2kw higig pause frame EP2AGX65 EP2AGX65DF29 HDTV transmitter receivers block diagram 32-Bit Parallel-IN Serial-OUT Shift Register prbs parity checker and generator SILICON General 741 PMD Motion
|
Original |
||
EP3SL340F1517
Abstract: altera cyclone 3 handbook texas instruments HC335FF1152 HC325Ff DDR3 jedec diode handbook fbga Substrate design guidelines hc335 texas instruments handbook
|
Original |
||
lpddr2
Abstract: lpddr2 datasheet lpddr2 phy lpddr2 DQ calibration Datasheet LPDDR2 SDRAM DDR3L "Stratix IV" Package layout footprint HSUL-12 lpddr2 tutorial Verilog code of 1-bit full subtractor
|
Original |
2010Altera lpddr2 lpddr2 datasheet lpddr2 phy lpddr2 DQ calibration Datasheet LPDDR2 SDRAM DDR3L "Stratix IV" Package layout footprint HSUL-12 lpddr2 tutorial Verilog code of 1-bit full subtractor | |
EP4CE15
Abstract: EP4CE6 eqfp DIODE CQ 618 EP4CE115 EP4CE40 EP4CE75 ep4cgx110 ttl to mini-lvds EP4CE22 HSTL standards
|
Original |
CYIV-51006-2 EP4CE15 EP4CE6 eqfp DIODE CQ 618 EP4CE115 EP4CE40 EP4CE75 ep4cgx110 ttl to mini-lvds EP4CE22 HSTL standards | |
Contextual Info: CY7C4122KV13/CY7C4142KV13 144-Mbit QDR -IV XP SRAM 144-Mbit QDR™-IV GT SRAM Features • Configurations CY7C4122KV13 – 8 M x 18 144-Mbit density 8 M × 18, 4 M × 36 [1] ■ Total Random Transaction Rate of 2132 MT/s ■ Maximum operating frequency of 1066 MHz |
Original |
CY7C4122KV13/CY7C4142KV13 144-Mbit CY7C4122KV13 CY7C4142g | |
Contextual Info: CY7C4121KV13/CY7C4141KV13 144-Mbit QDR -IV HP SRAM 144-Mbit QDR™-IV HP SRAM Features • Configurations 144-Mbit density 8 M x 18, 4 M × 36 [1] CY7C4121KV13 – 8 M × 18 ■ Total Random Transaction Rate of 1334 MT/s ■ Maximum operating frequency of 667 MHz |
Original |
CY7C4121KV13/CY7C4141KV13 144-Mbit CY7C4121KV13 | |
Contextual Info: Arria II GX Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-2.0 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other |
Original |
||
5252 F 1105 transistor
Abstract: max 8770 TMS 3617 fa 5571 AS 12308 c 5296 Horizontal Output transistor, transistor c 5936 circuit diagram EP3C25 pin guideline tms 3878
|
Original |
||
EP2AGX260EF
Abstract: "switch power supply" handbook
|
Original |
||
TIMER FINDER TYPE 85.32
Abstract: tsmc design rule 40-nm FINDER TYPE 85.32 Texas Instruments Stratix IV EP4S series Power Ref Design 8 tap fir filter verilog FBP BGA
|
Original |
||
transistor 5503 dm
Abstract: hpc 3062 power module si 3101 schematic diagram HYBRID SYSTEMS ADC 560-3 lsp 5503 transistor horizontal c 5936 IC transistor linear handbook 4 pins jd 1803 transistor SI 6822
|
Original |
EP3SL50, EP3SL110, EP3SE80. transistor 5503 dm hpc 3062 power module si 3101 schematic diagram HYBRID SYSTEMS ADC 560-3 lsp 5503 transistor horizontal c 5936 IC transistor linear handbook 4 pins jd 1803 transistor SI 6822 | |
|
|||
Contextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V1-1.4 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and |
Original |
||
KF35-F1152
Abstract: 5SGX receiver altLVDS vhdl code scrambler epcq "switch power supply" handbook CD 76 13 CP
|
Original |
||
A1GKContextual Info: Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SIII5V1-1.0 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and |
Original |
1760-pin 760-Pin A1GK | |
EP3C80F484C6N
Abstract: diode DIN 4148 0441 EP3C55F484C8N EP3C25E144C7 EP3C16F484I7 EP3C25U256C7N EP3C5E144 EP3C16Q240C8N EP3C80F780C8N EP3C25E144
|
Original |
EP3C10 EP3C10F256I7 EP3C10U256C6 EP3C10U256C6N EP3C10U256C7 EP3C10U256C7N EP3C10U256C8 EP3C10U256C8N EP3C10 EP3C80F484C6N diode DIN 4148 0441 EP3C55F484C8N EP3C25E144C7 EP3C16F484I7 EP3C25U256C7N EP3C5E144 EP3C16Q240C8N EP3C80F780C8N EP3C25E144 | |
tsmc design rule 40-nmContextual Info: Stratix IV Device Handbook Volume 1 Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.2 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. |
Original |
||
vhdl code for 1 bit error generatorContextual Info: Cyclone IV Device Handbook, Volume 1 Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.9 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos |
Original |
||
Contextual Info: Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.6 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as |
Original |
||
9a21Contextual Info: Arria II Device Handbook Volume 1: Device Interfaces and Integration Arria II Device Handbook Volume 1: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V1-4.4 Document last updated for Altera Complete Design Suite version: |
Original |
||
Contextual Info: Cyclone IV Device Handbook, Volume 1 Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.9 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos |
Original |
||
Contextual Info: Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.6 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as |
Original |