JEDEC SOP CASE OUTLINE Search Results

JEDEC SOP CASE OUTLINE Result Highlights (5)

Part	Manufacturer	Description
TPH9R00CQH	Toshiba Electronic Devices & Storage Corporation	MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N)
TPH9R00CQ5	Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 150 V, 64 A, 0.009 Ω@10 V, High-speed diode, SOP Advance / SOP Advance(N)
TPH1R306PL	Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 60 V, 100 A, 0.00134 Ω@10 V, SOP Advance / SOP Advance(N)
TPHR8504PL	Toshiba Electronic Devices & Storage Corporation	N-ch MOSFET, 40 V, 150 A, 0.00085 Ω@10 V, SOP Advance / SOP Advance(N)
TPH2R408QM	Toshiba Electronic Devices & Storage Corporation	MOSFET, N-ch, 80 V, 120 A, 0.00243 Ohm@10V, SOP Advance

JEDEC SOP CASE OUTLINE Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
IPC-J-STD-001 Abstract: TRAY DAEWON TSOP 6n1 tube IPC-JSTD-001 VHH10-6N1 Intel Corporation esd flash small outline package guide DAEWON tray 48 optical Pick-Up head venturi meter R08-01-FOGO Text: Intel-Recommended Manual Handling/Programming Process for Small Outline Packages Version 2.5 CONTENTS Section Title Page 1.0 Scope 2 2.0 Introduction 2 3.0 Applicable Documents 2 4.0 Work Area/Station Setup 2 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Programming Process Procedures	Original		PDF
DAEWON tray tsop 48LD Abstract: nikon v12B 6n1 tube IPC-J-STD-001 nikon GRAINGER TRAY TSOP 56LD daewon TRAY DAEWON TSOP venturi meter Text: Intel-Recommended Manual Handling/Programming Process for Small Outline Packages Version 2.4 CONTENTS Section Title Page 1.0 Scope 2 2.0 Introduction 2 3.0 Applicable Documents 2 4.0 Work Area/Station Setup 2 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Programming Procedures	Original		PDF
Datasheet of IC 7432 Abstract: 7415 ic pin details data sheet IC 7432 DATASHEET OF IC 7401 7401 ic configuration IC 7409 draw pin configuration of ic 7402 INFORMATION OF IC 7424 BGA and QFP Package mounting EIA and EIAJ standards Text: CHAPTER 1 CHAPTER 1 1.1 PACKAGE OUTLINES AND EXPLANATION PACKAGE OUTLINES AND EXPLANATION Types of Packages 1.1.1 Classification of IC packages The following figure classifies the packages for semiconductor products: SDIP DIP QUIP SIP ZIP Through hole mount type	Original		PDF
land pattern for TSOP 2-44 Abstract: Wells programming adapter TSOP 48 intel 44-lead psop land pattern for TSOP 56 pin F9232 E28F016SA70 tsop tray matrix outline wells 648-0482211 memory card thickness 29f200 tsop adapter Text: D Small Outline Package Guide 1996 296514-006 8/19/97 5:26 PM FRONT.DOC Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions	Original		PDF
TSOP-48 pcb LAYOUT Abstract: str 6654 pin details of str f 6654 pin details of str W 6654 amd socket 940 pinout str W 6654 land pattern tsop 66 56-Lead TSOP Package 28F002BC 28F010 Text: D Small Outline Package Guide 1996 296514-006 8/19/97 5:26 PM FRONT.DOC Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions	Original		PDF
pioneer PAL 007 A Abstract: PAL 007 pioneer str 6654 PAL 008 pioneer pin details of str W 6654 sem 2106 Yamaichi Electronics ic197 648-0482211 TSOP56 jackson Text: D Small Outline Package Guide 1999 3/25/99 4:28 PM cvrpg.doc Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions	Original		PDF
PAL 007 pioneer Abstract: pioneer PAL 007 A PAL 008 pioneer sn 7600 n 648-0482211 sem 2106 Trays tsop56 TSOP 86 land pattern amd socket 940 pinout Meritec 980020-56 Text: D Small Outline Package Guide 1999 3/25/99 4:28 PM cvrpg.doc Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions	Original		PDF
Untitled Abstract: No abstract text available Text: 4 PIN SOP PHOTOTRANSISTOR PHOTOCOUPLER AC INPUT PHOTOCOUPLE EL354N-G Series Schematic Features: • Halogens free • Current transfer ratio CTR: Min. 20% at IF =±1mA ,VCE =5V • High isolation voltage between input and output • Compact small outline package	Original	EL354N-G E214129) DPC-0000116	PDF
SOT23W-3 Abstract: transistor crossreference footprint soic 16 soic pcb footprint DFN 10 socket EK QFN MS-018AC qfn 44 PACKAGE footprint qsop 16 pcb footprint SOT23 MARK EW Text: Product Information Allegro Package Designations This document provides reference information as an aid to differentiating the device package types used by Allegro MicroSystems. It provides cross references to the package designation, an Allegro code that is integrated into the device part number:	Original	PUB26013 SOT23W-3 transistor crossreference footprint soic 16 soic pcb footprint DFN 10 socket EK QFN MS-018AC qfn 44 PACKAGE footprint qsop 16 pcb footprint SOT23 MARK EW	PDF
MM74HC4094 Abstract: MM74HC4094N MM74HC4094M MM74HC4050M soic 16 Jedec package outline 74HC CD4049BC CD4050BC MM74HC4049 MM74HC4050 Text: Revised February 1999 MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter General Description The MM74HC4049 and the MM74HC4050 utilize advanced silicon-gate CMOS technology, and have a modified input protection structure that enables these parts to	Original	MM74HC4049 MM74HC4050 MM74HC4049 MM74HC4050 MM74HC4094 MM74HC4094N MM74HC4094M MM74HC4050M soic 16 Jedec package outline 74HC CD4049BC CD4050BC	PDF
MM74HC125M Abstract: 74HC MM74HC125 MM74HC125MTC MM74HC125MTCX-NL MM74HC125N MM74HC125SJ MM74HC126 MM74HC126M Text: Revised January 2005 MM74HC125/MM74HC126 3-STATE Quad Buffers General Description Features The MM74HC125 and MM74HC126 are general purpose 3-STATE high speed non-inverting buffers utilizing advanced silicon-gate CMOS technology. They have high drive current outputs which enable high speed operation	Original	MM74HC125/MM74HC126 MM74HC125 MM74HC126 MM74HC125M 74HC MM74HC125MTC MM74HC125MTCX-NL MM74HC125N MM74HC125SJ MM74HC126M	PDF
and pin diagram of cd4020 Abstract: cd4020 pin diagram pin diagram of cd4040 CD4020 description and pin diagram of cd4020 cd4040 dip CD4040 PIN DIAGRAM pin Diagram cd4040 CD4040 circuit diagram of cd4040 Text: Revised February 1999 MM74HC4020 • MM74HC4040 14-Stage Binary Counter • 12-Stage Binary Counter General Description The MM74HC4020, MM74HC4040, are high speed binary ripple carry counters. These counters are implemented utilizing advanced silicon-gate CMOS technology to achieve	Original	MM74HC4020 MM74HC4040 14-Stage 12-Stage MM74HC4020, MM74HC4040, MM74HC4020 MM74HC4040 CD4020 and pin diagram of cd4020 cd4020 pin diagram pin diagram of cd4040 description and pin diagram of cd4020 cd4040 dip CD4040 PIN DIAGRAM pin Diagram cd4040 CD4040 circuit diagram of cd4040	PDF
JEDEC MO 224 Abstract: MM74HC541N 74HC MM74HC540 MM74HC540MTC MM74HC540N MM74HC540SJ MM74HC540WM MM74HC541 MM74HC541MTC Text: Revised February 1999 MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate CMOS technology. They possess high drive current outputs which enable high speed	Original	MM74HC540 MM74HC541 MM74HC540 MM74HC541 JEDEC MO 224 MM74HC541N 74HC MM74HC540MTC MM74HC540N MM74HC540SJ MM74HC540WM MM74HC541MTC	PDF
MM74HC4051N Abstract: MM74HC4053N MM74HC4051 MM74HC4052 hc4051 74HC MM74HC4051M MM74HC4051MTC MM74HC4051SJ MM74HC4051WM Text: Revised May 1999 MM74HC4051 • MM74HC4052 • MM74HC4053 8-Channel Analog Multiplexer • Dual 4-Channel Analog Multiplexer • Triple 2-Channel Analog Multiplexer General Description The MM74HC4051, MM74HC4052 and MM74HC4053 multiplexers are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology. These	Original	MM74HC4051 MM74HC4052 MM74HC4053 MM74HC4051, MM74HC4052 MM74HC4053 MM74HC4051N MM74HC4053N MM74HC4051 hc4051 74HC MM74HC4051M MM74HC4051MTC MM74HC4051SJ MM74HC4051WM	PDF

MM74HC32N Abstract: 74HC 74LS M14A MM74HC32 MM74HC32M MM74HC32MTC MM74HC32MTCX MM74HC32MX MM74HC32SJ Text: Revised January 2005 MM74HC32 Quad 2-Input OR Gate General Description Features The MM74HC32 OR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs	Original	MM74HC32 MM74HC32 MM74HC32N 74HC 74LS M14A MM74HC32M MM74HC32MTC MM74HC32MTCX MM74HC32MX MM74HC32SJ	PDF
74HC Abstract: MM74HC540 MM74HC540MTC MM74HC540N MM74HC540SJ MM74HC540WM MM74HC541 MM74HC541MTC MM74HC541SJ MM74HC541WM Text: Revised May 2005 MM74HC540 • MM74HC541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer General Description Features The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate CMOS technology. They possess high drive current outputs which enable high speed	Original	MM74HC540 MM74HC541 MM74HC540 MM74HC541 74HC MM74HC540MTC MM74HC540N MM74HC540SJ MM74HC540WM MM74HC541MTC MM74HC541SJ MM74HC541WM	PDF
MM74HC00 Abstract: mm74hc00m MM74HC00SJ MM74HC00MX_NL 74HC 74LS M14A MM74HC00MTC MM74HC00MTCX MM74HC00MX Text: Revised January 2005 MM74HC00 Quad 2-Input NAND Gate General Description Features The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs.	Original	MM74HC00 MM74HC00 mm74hc00m MM74HC00SJ MM74HC00MX_NL 74HC 74LS M14A MM74HC00MTC MM74HC00MTCX MM74HC00MX	PDF
74HCU Abstract: 74LS M14A M14D MM74HCU04 MM74HCU04M MM74HCU04MTC MM74HCU04MX MM74HCU04N MM74HCU04SJ Text: Revised January 2005 MM74HCU04 Hex Inverter General Description Features The MM74HCU04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits.	Original	MM74HCU04 MM74HCU04 74HCU 74LS M14A M14D MM74HCU04M MM74HCU04MTC MM74HCU04MX MM74HCU04N MM74HCU04SJ	PDF
MM74HC04 Abstract: MM74HC04M Logic Circuit, HEX Inverter, CMOS, 14 Pin, Plastic, SOP MM74HC04M_NL 74HC 74LS M14D MM74HC04MTC MM74HC04N MM74HC04SJ Text: Revised January 2005 MM74HC04 Hex Inverter General Description Features The MM74HC04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits.	Original	MM74HC04 MM74HC04 MM74HC04M Logic Circuit, HEX Inverter, CMOS, 14 Pin, Plastic, SOP MM74HC04M_NL 74HC 74LS M14D MM74HC04MTC MM74HC04N MM74HC04SJ	PDF
MM74HC02 Abstract: MM74HC02N 74HC 74LS M14A M14D MM74HC02M MM74HC02MTC MM74HC02MTCX MM74HC02SJ Text: Revised January 2005 MM74HC02 Quad 2-Input NOR Gate General Description Features The MM74HC02 NOR gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs,	Original	MM74HC02 MM74HC02 MM74HC02N 74HC 74LS M14A M14D MM74HC02M MM74HC02MTC MM74HC02MTCX MM74HC02SJ	PDF
74HCT Abstract: 74LS M14A M14D MM74HCT14 MM74HCT14M MM74HCT14MTC MM74HCT14N MM74HCT14SJ MTC14 Text: Revised February 1999 MM74HCT14 Hex Inverting Schmitt Trigger General Description Features The MM74HCT14 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability	Original	MM74HCT14 MM74HCT14 74HCT 74LS M14A M14D MM74HCT14M MM74HCT14MTC MM74HCT14N MM74HCT14SJ MTC14	PDF
74HCT Abstract: 74LS M14A M14D MM74HCT14 MM74HCT14M MM74HCT14MTC MM74HCT14MX MM74HCT14N MM74HCT14SJ Text: Revised January 2005 MM74HCT14 Hex Inverting Schmitt Trigger General Description Features The MM74HCT14 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability	Original	MM74HCT14 MM74HCT14 74HCT 74LS M14A M14D MM74HCT14M MM74HCT14MTC MM74HCT14MX MM74HCT14N MM74HCT14SJ	PDF
MM74HC14M Abstract: mm74hc14n MM74HC14SJ 74HC 74LS M14A MM74HC14 MM74HC14MTC MM74HC14MTCX MM74HC14MX Text: Revised May 2005 MM74HC14 Hex Inverting Schmitt Trigger General Description Features The MM74HC14 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability to drive 10 LS-TTL loads.	Original	MM74HC14 MM74HC14 MM74HC14M mm74hc14n MM74HC14SJ 74HC 74LS M14A MM74HC14MTC MM74HC14MTCX MM74HC14MX	PDF
Untitled Abstract: No abstract text available Text: 0.216 FR EE S C A L E SEMICOND UCTOR, ALL R I GH TS RESERVED. INC. MECHANICAL OUTLINE TITLE: 8 LD SOP, GVP PRINT VERSION NOT TO SCALE DOCUMENT NO: 98A S A 99302D REV: C CASE NUMBER: 1368-01 18 DEC 2 008 STANDARD: NON-JEDEC D ETA IL ”G” © FR EE S C A L E SEMICOND UCTOR,	OCR Scan	98ASA99302D 5M-1994. 98ASA99302D	PDF

JEDEC SOP CASE OUTLINE Search Results

JEDEC SOP CASE OUTLINE Result Highlights (5)

JEDEC SOP CASE OUTLINE Datasheets Context Search

IPC-J-STD-001

DAEWON tray tsop 48LD

Datasheet of IC 7432

land pattern for TSOP 2-44

TSOP-48 pcb LAYOUT

pioneer PAL 007 A

PAL 007 pioneer

Untitled

SOT23W-3

MM74HC4094

MM74HC125M

and pin diagram of cd4020

JEDEC MO 224

MM74HC4051N

MM74HC32N

74HC

MM74HC00

74HCU

MM74HC04

MM74HC02

74HCT

74HCT

MM74HC14M

Untitled