Motorola AN-913
Abstract: 2791L M68000 MCF5102 9222L c2 sub
Text: SECTION 9 INSTRUCTION TIMINGS This section summarizes instruction timings for the MCF5102. Table 9-1 alphabetically lists instruction timings and their location in this section. Table 9-1. Instruction Timing Index Instruction Page Instruction Page Instruction
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MCF5102.
MCF5102
Motorola AN-913
2791L
M68000
9222L
c2 sub
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hitachi sh4
Abstract: hitachi graphics accelerator HD64465 codescape SH7750 EBX7750 HD64461 STLC7546 STLC7550 hitachi video panel
Text: October 2000 The main features of the SH7750 SH-4 series are: ❚ 32-bit RISC load/store architecture ❚ 16-bit fixed instruction length for high code density ❚ 5-stage RISC instruction pipeline ❚ 2-way superscalar instruction execution ❚ 8 KB instruction cache
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SH7750
32-bit
16-bit
hitachi sh4
hitachi graphics accelerator
HD64465
codescape
EBX7750
HD64461
STLC7546
STLC7550
hitachi video panel
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DSP56000
Abstract: DSP56001
Text: APPENDIX A INSTRUCTION SET DETAILS This appendix contains detailed information about each instruction in the DSP56000/ DSP56001 instruction set. An instruction guide is presented first to help understand the individual instruction descriptions. This guide is followed by sections on notation and
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DSP56000/
DSP56001
DSP56000/DSP56001
DSP56000
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addressing modes in adsp-21xx
Abstract: addressing modes of adsp 21xx processors direct addressing mode in adsp-21xx ADSP-2100 digital signal processing using the ADSP-2100 processor shift register alu ADSP-2100 Family Assembler Tools
Text: Instruction Set Reference 15.1 15 QUICK LIST OF INSTRUCTIONS This chapter is a complete reference for the instruction set of the ADSP-2100 family. The instruction set is organized by instruction group and, within each group, by individual instruction. The list below shows all
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ADSP-2100
addressing modes in adsp-21xx
addressing modes of adsp 21xx processors
direct addressing mode in adsp-21xx
digital signal processing using the ADSP-2100
processor shift register alu
ADSP-2100 Family Assembler Tools
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DSP56001
Abstract: 56001 DSP56001 users manual DSP56000 000E-6
Text: Freescale Semiconductor, Inc. APPENDIX A INSTRUCTION SET DETAILS Freescale Semiconductor, Inc. This appendix contains detailed information about each instruction in the DSP56000/ DSP56001 instruction set. An instruction guide is presented first to help understand the
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DSP56000/
DSP56001
DSP56000/DSP56001
56001
DSP56001 users manual
DSP56000
000E-6
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TMS320C55X
Abstract: SPRU599A TMS320C5502 TMS320C55x UART SPRU374 SPRU375 instruction set of TMS320C55x TMS320C5509 TMS320C5510 SIM5502
Text: TMS320C55x INSTRUCTION SET SIMULATOR TECHNICAL OVERVIEW SPRU599A – JULY 2002 – REVISED NOVEMBER 2002 ● ● ● ● TMS320C55x CPU Full Instruction Set Architecture Execution – Pipeline Protection for Internal Registers and Memory Locations – Parallel Instruction Execution
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TMS320C55x
SPRU599A
TMS320C55xTM
C5510
C5502
SPRU599A
TMS320C5502
TMS320C55x UART
SPRU374
SPRU375
instruction set of TMS320C55x
TMS320C5509
TMS320C5510
SIM5502
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DSP96002
Abstract: Floating-Point Arithmetic floating point adder
Text: SECTION 6 INSTRUCTION SET AND EXECUTION 6.1 INTRODUCTION This chapter introduces the DSP96002 instruction set and instruction format. The complete range of instruction capabilities combined with the flexible addressing modes described in Chapter 5 provide a very
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DSP96002
DSP96002,
Floating-Point Arithmetic
floating point adder
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motorola 723
Abstract: motorola 714 motorola 724
Text: SECTION 7 INSTRUCTION TIMING This section describes instruction flow and the basic instruction pipeline in the RCPU, provides details of execution timing for each execution unit, defines the concepts of serialization and synchronization, provides timing information for each
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harvard architecture block diagram
Abstract: ARM9TDMI arm9tdmi block diagram harvard architecture processor block diagram AMI Semiconductor DSP ARM922T CP15 applications of arm processor
Text: ARM922T Embedded RISC Microcontroller Core 1.0 Features • 32-bit reduced instruction set computer RISC architecture • Five-stage pipeline consisting of fetch, decode, execute, memory and write stages • Two instruction sets: - ARM high-performance 32-bit instruction set
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ARM922T
32-bit
16-bit
ARM922T
harvard architecture block diagram
ARM9TDMI
arm9tdmi block diagram
harvard architecture processor block diagram
AMI Semiconductor DSP
CP15
applications of arm processor
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ldr datasheet
Abstract: ARM instruction set bpl modem 8 bit modified booth multipliers CODE16 KS32C6200 S5N8946
Text: S5N8946 ADSL/CABLE MODEM MCU 3 ARM INSTRUCTION SET INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core. FORMAT SUMMARY The ARM instruction set formats are shown below. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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S5N8946
udiv10
ldr datasheet
ARM instruction set
bpl modem
8 bit modified booth multipliers
CODE16
KS32C6200
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2431EA
Abstract: bcx 16 b2790 powerpc 476
Text: MPCxxx Instruction Set This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level s of the PowerPC architecture in which the instruction may
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DSP56K
Abstract: A-18
Text: INSTRUCTION TIMING A.8 INSTRUCTION TIMING This section describes how to calculate DSP56K instruction timing manually using the tables provided. Three complete examples illustrate the “layered’’ nature of the tables. Alternatively, the user can determine the number of instruction program words and the
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DSP56K
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DST80
Abstract: 3521H
Text: <P.75Â7UGT U /CPWCN #FFTGUU 5RCEG =L/2* INSTRUCTION DESCRIPTION AND FORMATS The following section lists each instruction set, and describes the: Instruction Format Operation performed Flag Conditions Examples of the code The format for the instruction uses the following conventions:
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1110B
11110000B)
01111111B)
10001111B)
11110111B)
00000111B)
01101100B)
01101001B)
DST80
3521H
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PowerPC 601 instructions set
Abstract: 2021ME
Text: MPCxxx Instruction Set This chapter lists the MPCxxx instruction set in alphabetical order by mnemonic. Note that each entry includes the instruction formats and a quick reference ‘legend’ that provides such information as the level s of the PowerPC architecture in which the instruction may
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Untitled
Abstract: No abstract text available
Text: RISCore32300TM Family Integrated Processor Featur tures 79RC32334 Advance Information* ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – MIPS32 Instruction Set Architecture ISA – Cache prefetch instruction – Conditional move instruction
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RISCore32300TM
79RC32334
RISCore32300
MIPS-32
RC5000
32-page
32-bit
RC32334
RC64144
RC64145
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jazelle
Abstract: ARM926EJ-S ARM926EJ CP15 ARM926EJ-STM
Text: Features • ARM9EJ-S Based on ARM Architecture v5TEJ with Jazelle® Technology • Three Instruction Sets • • • • • • • • • – ARM® High-performance 32-bit Instruction Set – Thumb® High Code Density 16-bit Instruction Set – Jazelle® 8-bit Instruction Set
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32-bit
16-bit
6128AS
11-Apr-05
jazelle
ARM926EJ-S
ARM926EJ
CP15
ARM926EJ-STM
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MIPS32 instruction set
Abstract: t8kb 79RC32334 MIPS32 RC32300 RC5000 RC64474
Text: RISCore32300TM Family Integrated Processor Featur tures 79RC32334 Preliminary Information* ◆ ◆ RC32300 32-bit Microprocessor – Up to 150 MHz operation – MIPS32 Instruction Set Architecture ISA – Cache prefetch instruction – Conditional move instruction
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RISCore32300TM
79RC32334
RC32300
32-bit
MIPS32
133MHz
150MHz
256-pin
IDT79RC32
MIPS32 instruction set
t8kb
79RC32334
RC5000
RC64474
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Untitled
Abstract: No abstract text available
Text: Instruction Set - Summary 4.0 Instruction Set 4.1 Instruction Set Summary A summary of the ARM710 instruction set is shown in Figure 7: Instruction Set Summary. Note: some instruction codes are not defined but do not cause the Undefined instruction trap to be taken,
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ARM710
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TAG 9109
Abstract: ande RY 227 powerpc 460 j526 MCEE IC JRC 1086 MPCFPE MPC500 texas instrument Motorola 9151
Text: POWE M P C 5 0 0 F a m ily RCPU Reference M anual M : MOTOROLA PowerPC' Microcontrollers OVERVIEW REGISTERS OPERAND CONVENTIONS ADDRESSING MODES AND INSTRUCTION SET SUMMARY INSTRUCTION CACHE EXCEPTIONS INSTRUCTION TIMING DEVELOPMENT SUPPORT INSTRUCTION SET
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MPC500
TAG 9109
ande RY 227
powerpc 460
j526
MCEE
IC JRC 1086
MPCFPE
texas instrument
Motorola 9151
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Untitled
Abstract: No abstract text available
Text: SHARP SM8311/SM8313/SM8314/SM8315 The SM83CPU core uses pipeline method to speed instruction execution. With this method, OP Exceptions are the memory access instruction and jump instruction : while in the execution cycle of code fetching cycle and execution cycle are
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SM8311/SM8313/SM8314/SM8315
SM83CPU
SM8311/13
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80960SA
Abstract: 80960SB 80960
Text: Instruction Set g CHAPTER 9 INSTRUCTION SET This chapter provides an overview of the instruction set for the 80960SA/SB processor. Included is a discussion of the instruction format, a summary of the instruction groups and the instructions in each group. This chapter gives detailed descriptions of each of the instructions. The instructions are listed
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80960SA/SB
80960SA
80960SB
80960
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M68000
Abstract: MC68000 MC68030 fpu coprocessor mc68000 programmer pipeline synchronization DM 321 MC68000PM MC68000PM/AD
Text: SECTION 3 INSTRUCTION SET SUMMARY This section briefly describes the MC68030 instruction set. Refer to the MC68000PM/AD, MC68000 Programmer's Reference Manual, for complete details on the MC68030 instruction set. The following paragraphs include descriptions of the instruction format and the operands
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MC68030
MC68000PM/AD,
MC68000
M68000
fpu coprocessor
mc68000 programmer
pipeline synchronization
DM 321
MC68000PM
MC68000PM/AD
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integer arithmetic
Abstract: MCF5200
Text: SECTION 3 INSTRUCTION SET SUMMARY This section briefly describes the ColdFire Family instruction set, using Motorola’s assembly language syntax and notation. It includes instruction set details such as notation and format, selected instruction examples, and an integer condition code discussion. The section
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MCF5200
integer arithmetic
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jalr
Abstract: UPD30111 DSRL32 mips16 instruction set
Text: ¿¿PD30111 NEC 22. INSTRUCTION SET The V r4111 has two types of instructions: 32-bit instructions MIPS III and 16-bit instructions (MIPS16). 22.1 MIPS III Instruction Each instruction of the MIPS III consists of 1 word (32 bits) located at a word boundary. Three instruction formats
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r4111
32-bit
16-bit
MIPS16)
uPD30111
jalr
DSRL32
mips16 instruction set
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