IND 449 Search Results

Contextual Info: MP, i 0 PRELIMINARY IND: -25 a PALLV22V1OZ-25 Advanced Micro Devices Low-Voltage, Zero-Power 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC compatible ■ Zero-power CMOS technology — 15 jiA standby current

P0168

Contextual Info: a IND: -15 PALCE22V1OZ-15 Zero-Power 24-Pin EE CMOS Versatile PAL Device Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Zero-power CMOS technology — 30 nA standby current — As fast as 15 ns first-access propagation delay and 50 MHz fMAx external

Contextual Info: gn National ÆÆ Semiconductor 54F/74F40 Dual 4-Input NAND Buffer General Description This device co ntains tw o ind ependent gates, each o f w hich perform s th e logic N AND function. Ordering Code: seesection5 Connection Diagrams Logic Symbol Pin A ssignm ent

Contextual Info: MÄV i o 1993 IND: -30 Advanced Micro Devices PALLV16V8Z-30 Low-Voltage, Zero-Power 20-Pin EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC compatible — Vcc = +3.0 V to +3.6 V ■ Zero-power CMOS technology

tt 3043 Transistor 5 pin type

Abstract: transistor sj 3161 transistor TT 3043 SCR K 3155 transistor NTE3090 NTE519 NTE3078 scr nte 480 NTE cross 160A TRIAC
Contextual Info: N T E ELECTRONICS INC S5E T> bM aiSST DQQEbfl? STS « N T E T-H \-*O I D INDICATORS NTE TVI» No. Description and Application Dtag. NO. «y Per Bag Ind Pkg S ia Typical Viewing Angle Viewed ' Color Typical Maximum (Volts) Breakdown voltage (Vorta) Maximum

P0168

Abstract: 30a48
Contextual Info: FINAL IND: -25 a PALLV22V1OZ-25 Advanced Micro Devices Low-Voltage, Zero-Power 24-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHARACTERISTICS • Low-voltage operation, 3.3 V JEDEC compatible ■ Zero-power CMOS technology — 30 ¿A standby current — 25 ns first-access propagation delay

Contextual Info: IND 006 Effective: 11/15/2011 PREFERRED DISTRIBUTOR PRICE LIST Copper will escalate/de-escalate at time of order shipment Comex Copper Base $3.25 PART NUMBER AWG SIZE Copper Weight/MFT PRICE/MFT 9 12 17 30 12 18 25 46 18 27 37 71 $225 $266 $349 $551 $272 $335

Contextual Info: OUTLINE DRAWINGS ORIENTATION IND CATOR \~ - .800 - H Outline 101 Outline 102 Outline 103 Outline 104 Miscellaneous V - ORIENTATION INDICATOR Outline 105 P u l s a r M i c r o w a v e C o r p o r a t i o n OUTLINE DRAWINGS 48 Industrial West ♦ Clifton, N J 07012

T10X5X5

Abstract: EER54 EE55B
Contextual Info: Magnetic Material Ind . Co., LTD Introduction & Characteristics of MnZn Ferrite cores Page1-12 Mnzn Power Material EER,ETD,RM,UYF,EP,EPC,UY,EFD,LP Page13-18 PQ,URS,UF&UI,ED,T,EI,EE Page19-26 Mnzn High Permeability Material EE,EI,EP,FT&ET,UF&UI,T,RM, Common mode choke cores applied in EMS,ET

pin configuration IC 74151

Abstract: IC 74151 diagram and truth table IC TTL 7400 diagram and truth table ic 74151 full adder using Multiplexer IC 74151 Multiplexer IC 74151 programmer manual EPLD cypress IC 7400 SERIES ALL DATA programming manual EPLD cy7c342
Contextual Info: CYPRESS SEMICONDUCTOR HOE D 256*^2 DD05427 5 ICYP 7 T V d -/3 -4 7 CY7C340 EPLD Family « 1 ^ CYPRESS SEMICONDUCTOR Multiple Array Matrix High-Density EPLDs Features General Description • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions

LCMX0640

Abstract: LCMXO2280C-3T144C LCMXO640C-3TN100I LCMXO2280E-3TN100I LCMXO1200C-3T144I LCMXO640C-4TN144C LCMXO256C-3TN100I LCMXO1200C LCMXO256C-3TN100C 3TN100C
Contextual Info: MachXO Family Data Sheet Version 01.0, July 2005 MachXO Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: MachXO Family Data Sheet Version 01.1, October 2005 MachXO Family Data Sheet Introduction October 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

LFEC1E-3Tn100C

Abstract: DDR400 LFEC10 LFEC15 LFEC33 LFECP10 LFECP15 LFECP20 LFECP33 LFEC1E-3TN144I
Contextual Info: LatticeECP/EC Family Data Sheet Version 01.4, December 2004 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features − − − − − − • Extensive Density and Package Options • 1.5K to 41K LUT4s • 65 to 576 I/Os

Contextual Info: LatticeXP Family Data Sheet Version 04.4, April 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

Contextual Info: LatticeXP Family Data Sheet DS1001 Version 05.0, July 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

LFXP3C-3TN144C

Abstract: LFXP6C-4FN256C 3FN3 LFXP3C-3TN100C LFXP6C-3FN256I PT36 LFXP10C-3F256I LFXP3C-4TN100C LFXP15C-5FN388C LFXP6
Contextual Info: LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

PL44A

Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.9, February 2007 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

PT15B

Abstract: LFXP20C-5FN484C
Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.9, February 2007 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

LFXP10C-4FN256C

Abstract: PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C
Contextual Info: LatticeXP Family Data Sheet Version 04.5, May 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

LFXP20C-5F256C

Abstract: LFXP20C-4F484C PT15B
Contextual Info: LatticeXP Family Data Sheet DS1001 Version 05.1, November 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001  Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces:  LVCMOS 3.3/2.5/1.8/1.5/1.2

LFXP20C-4F484C

Abstract: PT15B
Contextual Info: LatticeXP Family Data Sheet Version 04.3, March 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL

lfe2

Abstract: PL25B
Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.6, April 2007 LatticeECP2/M Family Data Sheet Introduction April 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic

Contextual Info: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2

Contextual Info: LatticeXP Family Data Sheet Version 04.0, December 2005 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL