IDD25 Search Results

A1515-1

Contextual Info: EtherMap -48 Device OC-48 SONET/SDH Ethernet Mapper TXC-06710 TECHNICAL OVERVIEW PRODUCT PREVIEW TERMINAL SIDE Control & Clock EEPROM Signals Serial Interface EtherMap™-48 TXC-06710 is a highly-integrated device for mapping IEEE 802.3 100/1000 Mbps Ethernet and block encoded

MC 4011 BCP

Abstract: PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT
Contextual Info: EtherPHAST -24 Device 2x OC-12/STM-4 SONET/SDH Ethernet Mapper TXC-06745 DATA SHEET TXC-06745-MB, Ed. 2 February 2006 FEATURES APPLICATIONS • Client Interfaces: 2x GMII/24x SMII/4x TBI/MPI 24 channel packet all pin shared • Two serial Gigabit Ethernet (1.25 Gbit/s) ports with integrated CRSU/SerDes (8B/10B)

IS61DDB21M36

Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

K7D803671B-HC33

Abstract: K7D803671B-HC30 K7D801871B-HC35 K7D801871B-HC37 K7D803671B K7D803671B-HC25 K7D803671B-HC35 K7D803671B-HC37
Contextual Info: K7D803671B K7D801871B 256Kx36 & 512Kx18 SRAM Document Title 8M DDR SYNCHRONOUS SRAM Revision History Rev No. History Draft Data Remark Rev. 0.0 -Initial document. July. 2000 Advance Rev. 0.1 -ZQ tolerance changed from 10% to 15% Aug. 2000 Advance Rev. 0.2

stanag 3910

Abstract: STANAG 3838 stanag 1553B MCT83100 MCT83102 CW10 MCT83102-3 MCT83103 MCT83910
Contextual Info: Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ MCT83100 Series

nrzi Decoder

Abstract: DS32EL0124 DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ
Contextual Info: DS32EL0124, DS32ELX0124 125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface General Description Features The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and

DS32ELX0124SQE

Abstract: DS32EL0124 dvi-d 24 pin diagram DS32EL0124SQ DS32EL0124SQE DS32EL0124SQX DS32ELX0124 DS32ELX0124SQ
Contextual Info: DS32EL0124, DS32ELX0124 125 MHz — 312.5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface General Description Features The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and

dvi-d 24 pin diagram

Abstract: DS32EL0421 DS32ELX0421 SDI scrambler DVI-D Single Link
Contextual Info: DS32EL0421, DS32ELX0421 125 – 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface General Description Features The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz DDR serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical

Contextual Info: K7P323674C K7P321874C 1Mx36 & 2Mx18 SRAM 36Mb Late Write SRAM Specification 119BGA with Pb & Pb-Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

BUS- STANAG-3910

Abstract: stanag 3910
Contextual Info: GEC P L E S S E Y I s e m i c o n d u c t o r s ! 3033-1.3 November 1991 MCT83100 Series MIL-STD-1553B STANAG 3838 REMOTE TERMINAL UNIT Supersedes H 1 0 4 0 1F U G all versions The MCT83100 series is a range of complete dual redundant MIL-STD-1553B (STANAG 3838) Remote

Contextual Info: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     512Kx36 and 1Mx18 configuration available.

Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . ISSI March 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

K7P161866M-HC30

Contextual Info: K7P163666M K7P161866M 512Kx36 & 1Mx18 SRAM Document Title 512Kx36 & 1Mx18 Synchronous Pipelined SRAM Revision History Rev. No. History Draft Date Remark Rev. 0.0 - Initial Document Apr. 2000 Advance Rev. 0.1 - Leakage current test condition changed from VDD to VDDQ

CY2281-11S

Abstract: block diagram of pentium PROCESSOR led running circuit electric O28 Package CY2281 CY2281PVC-1 CY2281PVC-11S
Contextual Info: fax id: 3552 CY2281-1 CY2281-11S PRELIMINARY 100MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs Features tems. A summary of clock outputs for both devices is shown below. • Mixed 2.5V and 3.3V operation • Complete clock solution for Pentium® II, and other similar processor-based motherboards

MAX3670

Abstract: STM-64 110GXS
Contextual Info: XPIO 110GXS Lowest Power 10G SERDES ! Fully Integrated 10Gbps Serializer/Deserializer Device February 2004 Data Sheet Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 269-pin flip-chip BGA 15 x 15 mm body size, 0.8 mm pitch

Contextual Info: K7P163666A K7P161866A Advance. 512Kx36 & 1Mx18 SRAM Document Title 512Kx36 & 1Mx18 Synchronous Pipelined SRAM Revision History Draft Date Remark - Initial Document Dec. 2001 Advance - Absolute maximum ratings are changed VDD : 2.815 - > 3.13 VDDQ : 2.815 - > 2.4

IDT77V1264L200

Contextual Info: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for

Contextual Info: DS32EL0421,DS32ELX0421 DS32EL0421, DS32ELX0421 125 - 312.5 MHz FPGA-Link Serializer with DDR LVDSParallel Interface Literature Number: SNLS282D DS32EL0421, DS32ELX0421 125 – 312.5 MHz FPGA-Link Serializer with DDR LVDS Parallel Interface General Description

IS61QDB21M18A

Contextual Info: IS61QDB21M18A IS61QDB251236A 1Mx18, 512Kx36 18Mb QUAD Burst 2 Synchronous SRAM FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window.

Contextual Info: IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                     2Mx36 and 4Mx18 configuration available. On-chip Delay Locked Loop (DLL) for wide data