IC 74LS138 PIN DIAGRAM Search Results

Ic 74hc138 logic diagram

Contextual Info: Revised February 1999 S E M IC Q N D U C T O R T M MM74HC138 3-to-8 Line Decoder The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equiva­ lent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to V qq and ground.

pin diagram of ic 74ls138

Abstract: 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function 74LS138 LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
Contextual Info: 74LS138, S138 Signetics Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Direct replacement for Intel 3205 74LS138

LOGIC OF 74LS138

Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin
Contextual Info: 74LS138, S138 Signetics Decoders/Dem ultiplexers 1-Of-8 D e co d e r/D e m u ltip le xe r Product Specification L o g ic P rod ucts FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding

l381

Abstract: and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138
Contextual Info: y SP74SC138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B • Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CMOS technology ■ Full TTL interface capability

74LS138PC

Contextual Info: 138 CONNECTION DIAGRAM PINOUT A & 54S/74S138 54LS/74LS138 bi f rC 1-0F-8 DECODER/DEMULTIPLEXER D E S C R IP TIO N — The '138 is a high speed 1-of-8 decoder/dem ultiplexer. This device is ideally suited for high speed bipolar memory chip select ad­ dress decoding. The m ultiple input enables allow parallel expansion to a

D133

Abstract: 74ls139 TTL 9334 74LS152 PIN 74LS42 7442 pin diagram 93L01 74156 ttl 74155 D132
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 T12 T11 T10 T9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

pin diagram of 74LS191

Abstract: TTL 7452 74155 74190 74151 74151 PIN DIAGRAM D132 74LS151 Logic DIAGRAM 74ls156 74191 state diagram
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D130 54/74190, 74LS190 54/74191, 74LS191 D132 54/74155, 54LS/74LS155 54/74156, 54LS/74LS156 D131 9321, 93L21, 54/74S139, 54LS/74LS139 15 14 13 T12 T11 T10 T9 Vcc = Pin 16 GND = Pin 8 Vcc = Pin 16 GND = Pin 8

connection diagram of ic 74ls138

Abstract: pin diagram of ic 74ls138 pin for 74LS138 74ls138 function sn54ls138 SN54LS13B 74LS138 function table ic 74ls138 74ls138 74S138A
Contextual Info: SN54LS13B, SN54S138, SN74LS138, SN74S13BA 3 LINE TO 8 UNE DECODERSjDEMULTIPLEXERS DECEMBER 1 9 7 2 -R E V IS E D M AR C H 1 9 8 8 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems SN 5 4 LS 1 38 , S N 54S 138 . . . J OR W PACKAG E

pin diagram of ic 74ls138

Abstract: ic 74ls138 motorola sn74ls138 o7ad motorola 74ls138 EM 5103
Contextual Info: MOTOROLA D E S C R IP T IO N — The L S T T L / M S I S N 5 4 L S / 7 4 L S 1 38 is a high speed 1-of-8 D ecoder/Dem ultiplexer. T h is device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1 -of-24 decoder using just three

connection diagram of ic 74ls138

Abstract: ic 74ls138 pin diagram of ic 74ls138 74LS138 3 to 8 decoder notes 74ls138 truth table
Contextual Info: MOTOROLA <8 > D E S C R I P T I O N — The L S T T L / M S IS N 5 4 L S / 7 4 L S 1 3 8 is a high speed 1-of-8 Decoder/Demultiplexer. This device is ideally suited for high speed bipolar m em ory chip select address decoding. The multiple input enables allow parallel expansion to a 1 -of-2 4 decoder u sing just three

SN54138

Abstract: SN74LS138 LS138 SN54LS138 SN54S138 SN74S138A gl 1151
Contextual Info: SN54LS138, SN54S138, SN74LS138, SN74S138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1972 — R E V IS E D M A R C H 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 54LS 138, S N 54S 138 SN 74LS 138, S N 74S 138A

64LS138

Contextual Info: S N 5 4 LS 13 8 , SN 54S138, S N 74 LS 13 8 , S N 74 S 13 8 A 3-LINE TO 8-LINE D EC OD ERS/DEM U LTIPLEXERS DECEMBER 1972 —REVISED MARCH 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems I I 3 Enable Inputs to Simplify Cascading

pin diagram of ic 74ls138

Abstract: FUNCTIONAL APPLICATION OF 74LS138 connection diagram of ic 74ls138 IC 74ls138 block diagram of 74LS138 3 to 8 decoder 74LS138 3 to 8 decoder notes 74LS138 HP5082-2835 MP7612 MP7612AP
Contextual Info: MP7612 Octal 12-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address µP Control Logic .the analog plus company TM FEATURES APPLICATIONS • Eight Independent 12-Bit DACs with Output Amplifiers • Low Power 320 mW typ. • Serial Digital Data and Address Port (3-Wire

ic 74ls138 pdf datasheet

Abstract: 74LS138 DATASHEET MP7610AS MP7610BP MP7610BS MP7610CP MP7610CS MP7611 HP5082-2835 MP7610
Contextual Info: MP7610 Octal 14-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address mP Control Logic June 1998-3 FEATURES • · · · · · · · · · APPLICATIONS Eight Independent 14-Bit DACs with Output Amplifiers Low Power 320 mW typ. Serial Digital Data and Address Port (3-Wire Standard)

7HC125

Abstract: ic 74ls138 block diagram of 74LS138 1 line to 16 line ic 74ls138 details ic 74ls138 pdf datasheet 74LS138 HP5082-2835 MC68000 MP7652 MP7652AN
Contextual Info: MP7652 4-Channel Voltage Output 15 MHz, Input Bandwidth, 8-Bit Multiplying DACs with 3-Wire Serial Digital Port and Independent References FEATURES • Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz • VREF/2 Output Preset Level • Latch-Up Free

pin diagram of ic 74ls138

Abstract: connection diagram of ic 74ls138 t138 FUNCTIONAL APPLICATION OF 74LS138 74HC138 M74HCT13
Contextual Info: M54HCT138 M74HCT138 SGS-THOMSON 3 TO 8 LINE DECODER INVERTING . HIGH SPEED tPD = 16 ns (TYP.) at Vcc = 5 V . LOW POWER DISSIPATION Ice = 4 (iA AT TA = 25 "C . OUTPUT DRIVE CAPABILITY 10LSTTL LOADS • BALANCED PROPAGATION DELAYS tpLH = tPHL B1R (Plastic Package)

8205 decoder

Abstract: 74LS138 decoder
Contextual Info: DAC811 For most current data sheet and other product information, visit www.burr-brown.com Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES ● SINGLE INTEGRATED CIRCUIT CHIP ● MICROCOMPUTER INTERFACE: Double-Buffered Latch ● VOLTAGE OUTPUT: ±10V, ±5V, +10V

block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line hp5082 7651 IC 74ls138 MP7651AS 74LS138 HP5082-2835 MC6800 MC68000 MP7651
Contextual Info: MP7651 8-Channel, Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Data Port and Chip Select Decoder FEATURES • 8 Independent 2-Quadrant Multiplying 8-Bit DACs • Serial Digital Input Data and Address Port 3-Wire Standard plus Internal Chip Address Decoder

EQUIVALENT 74HCT138

Abstract: T907 74HCT138 S-100-48 FUNCTIONAL APPLICATION OF 74LS138 G1.L 54HC 74HC M54HCT138 M74HCT138
Contextual Info: M54HCT138 M74HCT138 rZJ SGS -THOMSON RiOO [^@[i[L[lgT^ Q R!]ö(gS 3 TO 8 LINE DECODER LOW POWER DISSIPATION |cc = 4 aiA (MAX.) at TA = 25°C HIGH NOISE IMMUNITY Vnih = V N|L= 28% VCc (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

Contextual Info: Or, Cell Customer Service a 1 1-80Ú-548-6132 USA Only BURR-BROWN DAC811 AVAILABLE IN DIE 00 o < Q Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER 0) DC FEATURES • SINGLE INTEGRATED CIRCUIT CHIP • MICROCOMPUTER INTERFACE: DOUBLE-BUFFERED LATCH

7HC125

Abstract: 74LS138 HP5082-2835 MC68000 MP7641 MP7641AN MP7641AS MP7651 composite to sdi converter
Contextual Info: MP7641 8-Channel Voltage Output 10 MHz Input Bandwidth 8-Bit Multiplying DACs with Serial Digital Port FEATURES • DACs Matched to +0.5% typ • Chip Select Available: MP7651 • Low Harmonic Distortion: 0.25% typical with VREF = 1 V p-p @ 1 MHz • VREF/2 Output Preset Level

DAC811KU-1

Abstract: ic 74ls138 pdf datasheet DAC811 DAC811A DAC811AH DAC811BH DAC811J DAC811JP block diagram of 74LS138 3 to 8 decoder 74LS138 pin diagram
Contextual Info: DAC811 For most current data sheet and other product information, visit www.burr-brown.com Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES ● SINGLE INTEGRATED CIRCUIT CHIP ● MICROCOMPUTER INTERFACE: Double-Buffered Latch ● VOLTAGE OUTPUT: ±10V, ±5V, +10V

Contextual Info: C T S C S -T H O M S O N *7# dO g[i3 iLi(gra at VCc = 5V ■ LOW POWER DISSIPATION Ice = 4 at TA = 25°C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION DELAYS

M74HCT13

Contextual Info: Æ T SCS-TNOM SON *7# RÂlOMtlILIlÊ'irmDgi M54HCT138 M74HCT138 3 TO 8 LINE DECODER • LOW POWER DISSIPATION IC C = 4 f*A MAX. at TA = 25°C ■ HIGH NOISE IMMUNITY V n ih = VNIL= 28% VCc (MIN.) ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ SYMMETRICAL OUTPUT IMPEDANCE