I C 74LS76 Search Results

54S38

Abstract: SN74298 SN74265 54175 NES 1004 naval specification 74L95 Transistor AF 138 07802-1 SN7437 SN54LS195A
Contextual Info: m - G EN ER A L IN F O R M A TIO N INDEXES Numerical • Functional/Selection Guide O R D E R IN G INSTRUCTIO NS A N D M E C H A N IC A L D ATA 1 1 5 4/74 F A M IL Y SSI C IR CU ITS 2 I 54/74 F A M IL Y M S I/LSI C IR C U ITS 3 S E R IE S 29000 S S I C IR C U IT S

Jk 74ls76 pin out

Abstract: 74LS76 pinout TTL 74ls76 74ls76 74ls series logic family j-k flip flop 74ls76 LC74HC76 LC74HC76M 74LS76 dual flip-flop
Contextual Info: SANYO SE MIC ONDU CT OR CORP 1 2 E »"I 7Ti707b GQDEbbñ S tC 74HG76M r,: -.V . C M O S High-Speed Standard Logic L C 7 4 H C Senes 3035A Dual J -K Flip-Flop with Set and Reset 2186 Features • The LC 74H C 76M consists of 2 identical J-K type flip-flops.

74ls76a

Abstract: 74LS76AD
Contextual Info: M M O TO R O LA SNS4/74LS76A D E S C R I P T I O N — The S N 5 4 L S /7 4 L S 7 6 A offers individual J. K, Clock Pulse, D irect S et and Direct Clear inputs. These dual flip-flops are designed so that w h e n the clock goes HIGH, the inputs B re enabled and

100414DC

Abstract: 5401DM Fairchild dtl catalog fsa2719m 4727BPC FCM7010 FCM7004 937DMQB fairchild rtl FSA2501
Contextual Info: FAIRMONT ELECTRONICS PTY. LTD. TE L.48-6421 4 8 -6 4 8 1 /2 /4 C AB LES ' FAIRTRONICS' C R A IG H A L L T E L E X 8-3227 S A . P O .BOX 41102, C R A IG H A LL 2024. I ouani v-ox 39! 262Bramley 2018 FAIRCHILD 464 Ellis Street, M ountain View, C alifornia 94042

7475 D latch

Abstract: D146 D147 ci 7475 rs latch 74LS109 74LS78 74LS107 74LS114 7475 data latch
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| F I j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI l i l LiJ L il L iT I U LzJ Ll I ü ü bsJ QNO 9 3 4 li

74ls76 jk flip-flop logic symbol and truth table

Abstract: 7476PC 7476 PIN DIAGRAM 7476 truth table 74LS76PC 74LS76 dual flip-flop pin diagram of 7476 74LS76D 74LS76DC Jk 74ls76 pin out
Contextual Info: 76 CONNECTIO N DIAGRAM PINOUT A ^54/7476 OZZô/b> ^54H /74H 76 G f / c t l l/54LS/74LS76 DUAL JK FLIP-FLOP With Separate Sets, Clears and Clocks c p i [T DESCRIPTION — The ’76 and 'H76 are dual JK m aster/slave flip -flo p s with separate Direct Set, D irect Clear and Clock Pulse inputs fo r each flip -flop .

MA1002 digital LED Clock Module

Abstract: MA1002 Robinson Nugent CATALOG NSB7881 equivalent transistor P347 t110 94v 0 MEPCO 5043 LN543RA m7104 Lm13800
Contextual Info: D ID I-K E Y l r C O R P TOLL FREE W ATS LINE O R A T I O N Telephone Order Entry Now Available Until 7:00 P.M. Central Time I 1- 800- 344-4539 91 E A S Y TO R E M E M B E R : 1-800-DIGI-KEY A K , HI: 218-681 66741 Catalog No. 851 1Jan.-Fab., 11 HIGHWAY 32 SOUTH

74LS76

Abstract: flip-flop 74ls76 Jk 74ls76
Contextual Info: SANYO SE MIC ONDU CT OR CORP ~ 1EE I | 7Ti707b GODEbbñ fe-07-o 7 IC74HG76M •*- . .v_\ *•» C M O S High-Speed Standard Logic _ LC74H C Series . Dual J-K Flip-Flop with Set and Reset Features • The LC74HC76M consists o f 2 identical J-K type flip-flops.

Contextual Info: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES

dm8130

Abstract: 54175 DM74367 KS 2102 7486 ic truth table signetics 2502 ci 8602 gn block diagram ci 8602 gn 74s281 DM74LS76
Contextual Info: 19 7 6 N atio n al S e m ico n d u cto r C o rp . p 1 ? I m • ' % TTL Data Book D EV IC E MIL i 2502 2503 2504 5400 54H00 54L00 54LS00 5401 54H01 54L01 54LS01 5402 54L02 54LS02 5403 54L03 54LS03 5404 54H04 54L04 54LS04 5405 54H05 54L05 54LS05 5406 5407 5408

74LS167

Abstract: F199 transistor 74LS382 74LS514 74LS76A 74LS183 transistor b1100 74LS204 74ls171 F199
Contextual Info: L F U J I T S U M ICR OELECTRO N ICS • 76C D 13 374T?b2 0003=170 0 ■ n Î-4 2 -1 1 -0 5 " m zæm F U JIT S U @iÆ<§ ñ w m ^ is s E s i GENERAL INFORMATION •. o f standard SSI's and M STs such as 7 4 L S series are prepared as macros called " F - M A C R G " in the library.

TC74HC76

Abstract: 74LS76 IC TC74HC76AP
Contextual Info: TC74HC76AP/AF D U A L J - K F L I P - F L O P W IT H P R E S E T A N D C L E A R T h e T C 7 4 H C 7 6 A is a h ig h speed C M O S J - K F L IP FLO P fa b ric a te d w ith s ilic o n g a te C 2M O S tech n o lo g y. It ach ieve s the h ig h speed o p era tio n

7476 ic specifications

Abstract: ic 7476 IC 7476 JK logic diagram of ic 7476 7476 logic diagram 7476 ic
Contextual Info: SN547G, SN54LS76A, SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR D EC EM BE R 1 9 8 3 -R E V IS E D M A R C H • Dependable Texas Instruments Quality and Reliability TO P V IE W ] *^16 : i k iclkC 15 H 1 Q 1 prëC 2 14 : i q 1clrC 3 13 DGND

74LS76D

Abstract: M74HC76
Contextual Info: rrr s g s -th o m s o n Ä T # ms4 h c ? 6 R fflD O œ iL iO ÏÏM iD g i M 7 4 H C 7 6 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • HIG HSPEED fMAX = 65 MHz TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 2 jiA (MAX.) AT 25 °C ■ OUTPUT DRIVE CAPABILITY

N547A

Contextual Info: TYPES SN7476, SN74LS76A Q N547A 3N 5 4I S7 R A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR REVISED DECEMBER 1983 • • I Package Options Include Standard Plastic N and C eram ic (J) 300-m il D ual-ln -Lin e P ackages and P lastic S m all O u tlin e (D) Packages.

74LS76 IC

Abstract: TC74HC76AP IC 74LS76 AF4 equivalent TC74HC76A
Contextual Info: TC74HC76AP/AF D U A L J - K F L I P - F L O P WI TH P R E S E T A N D C L E A R The TC74HC76A is a high speed CMOS J - K FL IP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation sim ilar to equivalent LSTTL while m aintaining the CMOS low power

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC76P DUAL J-K F L IP -F L O P W IT H S E T AND R ESET DESCRIPTION The M 74H C 76 is a sem iconductor inte grated circu it con­ PIN CONFIGURATION TOP VIEW sisting of tw o n e g a tiv e -e d g e trig g e re d J -K flip flops w ith in­

logic ic 74LS76 pin diagram

Abstract: j-k flip flop 74ls76 IC 74LS76
Contextual Info: LS TTL DN74LS Series DN74LS76 D N 74LS76 D ^ 74^ 7^ Dual J-K F lip -F lo p s with S e t and Reset • Description P -2 D N 7 4 L S 7 6 contains tw o negative-edge triggered J-K flip-flop circuits, each w ith independent clock-C P, J, K, and directcoupled set and reset input terminals.

74ls

Abstract: N74LS764N
Contextual Info: Signelics 74LS764 DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL • Replaces 25 TTL devices to

A1266

Abstract: 16KX8 74LS 74LS764 N74LS764A N74LS764N PLCC-44
Contextual Info: 74LS764 S ignetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh

74LS764

Abstract: logic diagram and symbol of DRAM 74LS N74LS764A N74LS764N PLCC-44 18-BlT LS764
Contextual Info: 74LS764 Signetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh

MAX77100

Abstract: IC74 IC-74
Contextual Info: SANYO SEMICONDUCTOR CORP 53E TW OTb T> 0010S31 037 « T S A J r- H4>~ 0 7 — 0 7 MLC74HC76M No.3628 f CMOS High-Speed Standard Logic Dual J-K Flip-Flop with Reset and Set F e a tu re s • The MLC74HC76M consists of 2 identical J-K type flip-flops. • Uses CMOS silicon gate process technology to achieve operating speeds sim ilar to LS-TTL 74LS76

74LS764

Abstract: LS764
Contextual Info: 74LS764 Signetics DRAM Controller DRAM Dual-Ported Controller Product Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh

74LS

Abstract: 74LS765 N74LS765A N74LS765N PLCC-44
Contextual Info: 74LS765 Signetics DRAM Controller DRAM Dual-Ported Controller Preliminary Specification Logic Products FEATURES • Allows two microprocessors to access the same bank of DRAM • Replaces 25 TTL devices to perform arbitration, signal timing, multiplexing, and refresh