HIGH FREQUENCY FLIP FLOP Search Results

Contextual Info: SY10E131 SYNERG Y 4-BIT D FLIP-FLOP OTlUltlJl SEMICONDUCTOR DESCRIPTION FEATURES • 1100 MHz min. toggle frequency. The SY10E/100E/101E131 is a high speed quad master-slave D-type flip- flop with differential outputs designed for use in new high performance ECL systems. The flip-flops may be individually

DDD1173

Abstract: SY100E131 SY10E131
Contextual Info: * SYNERGY S E M IC O N D U C T O R SY10E131 SY100E131 4-BIT D FLIP-FLOP FEATURES DESCRIPTION 1100MHz min. toggle frequency The SY10/100E131 are high-speed quad m aster slave D-type flip-flops with differential outputs designed for use in new, high-perform ance ECL system s. The flip -flop s may

JK flip-flop

Abstract: master slave jk flip flop SY100EL35 SY100EL35ZC SY100EL35ZCTR SY10EL35 SY10EL35ZC SY10EL35ZCTR
Contextual Info: SY10EL35 SY100EL35 JK FLIP-FLOP FEATURES • ■ ■ ■ ■ DESCRIPTION 525ps propagation delay 2.2GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL35 are high-speed JK Flip-Flops. The

SY100EL35

Abstract: SY100EL35ZC SY100EL35ZCTR SY10EL35 SY10EL35ZC SY10EL35ZCTR
Contextual Info: SY10EL35 SY100EL35 FINAL JK FLIP-FLOP FEATURES • ■ ■ ■ ■ DESCRIPTION 525ps propagation delay 2.2GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL35 are high-speed JK Flip-Flops. The

HEL35

Abstract: MICREL marking
Contextual Info: SY10EL35 SY100EL35 FINAL JK FLIP-FLOP FEATURES • ■ ■ ■ ■ DESCRIPTION 525ps propagation delay 2.2GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package The SY10/100EL35 are high-speed JK Flip-Flops. The

Contextual Info: * HEX D FLIP-FLOP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 700MHz The SY100S351 offers six D-type, edge-triggered, m aster/slave flip-flops with differential outputs, and is designed for use in high-perform ance ECL system s. The

Contextual Info: « SY100S331 TRIPLE D FLIP-FLOP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Max. toggle frequency of 800MHz The SY100S331 offers three D-type, edge-triggered m aster/slave flip-flops with true and com plem ent outputs, designed for use in high-perform ance ECL system s. Each

74F04

Abstract: 751A-02 MC74F1803
Contextual Info: MOTOROLA Order this document from Logic Marketing SEMICONDUCTOR TECHNICAL DATA Advance Information Clock Driver Quad DĆType FlipĆFlop MC74F1803 With Matched Propagation Delays CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS The MC74F1803 is a high-speed, low-power, quad D-type flip-flop featuring separate D-type inputs and inverting outputs with closely matched propagation delays. With a buffered clock CP input that is common to all flipflops, the MC74F1803 is useful in high-frequency systems as a clock driver,

UPG700

Abstract: gaas D flip flop ic H16
Contextual Info: NEC UPG700B UPG700P MASTER/SLAVE D FLIP-FLOP OUTLINE DIMENSIONS FEATURES Units in mm OUTLINE H16 • LOGIC LEVELS AND SUPPLY VOLTAGES ARE ECL COMPATIBLE • ULTRA HIGH SPEED (Typ. O perating C lock Frequency-3.2 GHz) • HERMETICALLY SEALED PACKAGE ASSURES HIGH

HEL35

Abstract: SY100EL35 SY10EL35 SY10EL35LZC SY10EL35LZI SY10EL35LZITR
Contextual Info: Micrel, Inc. JK FLIP-FLOP FEATURES • ■ ■ ■ ■ SY10EL35 SY100EL35 SY10EL35 SY100EL35 DESCRIPTION 525ps propagation delay 2.2GHz toggle frequency High bandwidth output transistions Internal 75KΩ input pull-down resistors Available in 8-pin SOIC package

SY100E151

Abstract: SY10E151 SY10E151JC SY10E151JCTR
Contextual Info: 6-BIT D REGISTER FEATURES DESCRIPTION • 1100MHz toggle frequency ■ Extended 100E VEE range of –4.2V to –5.46V The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems.

Logic Level Gate Drive mosfet

Contextual Info: Supertex inc. CW01 Four-Channel, Low Phase Noise, Low Power, Continuous Wave Transmitter Features General Description The Supertex CW01 is a four-channel, low phase noise, continuous wave transmit IC. A high speed D flip-flop is provided to allow the DIN frequency to be aligned to a high

T Flip-Flop

Abstract: HMC729LC3C 0209 HIGH SPEED FREQUENCY DIVIDER Flip-Flop 1 ghz
Contextual Info: HMC729LC3C v03.0209 26 GHz, T TYPE FLIP-FLOP HIGH SPEED LOGIC - SMT 7 Typical Applications Features The HMC729LC3C is ideal for: Supports Clock Frequencies up to 26 GHz • Serial Data Transmission up to 26 Gbps Differential & Singe-Ended Operation • High Speed Frequency Divider up to 26 GHz

SY100E151

Abstract: SY10E151 SY10E151JC SY10E151JCTR
Contextual Info: SY10E151 SY100E151 FINAL 6-BIT D REGISTER FEATURES DESCRIPTION • 1100MHz toggle frequency ■ Extended 100E VEE range of –4.2V to –5.46V The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs, designed for use in new, high-performance ECL systems.

T Flip-Flop

Abstract: Flip-Flop 1 ghz
Contextual Info: HMC729LC3C v00.0608 26 GHz, T TYPE FLIP-FLOP HIGH SPEED LOGIC - SMT 7 Typical Applications Features The HMC729LC3C is ideal for: Supports Clock Frequencies up to 26 GHz • Serial Data Transmission up to 26 Gbps Differential & Singe-Ended Operation • High Speed Frequency Divider up to 26 GHz

CW-01

Abstract: PZT driver circuit
Contextual Info: Supertex inc. CW01 Four-Channel, Low Phase Noise, Low Power, Continuous Wave Transmitter Features General Description The Supertex CW01 is a four-channel, low phase noise, continuous wave transmit IC. A high speed D flip-flop is provided to allow the DIN frequency to be aligned to a high

T Flip-Flop

Abstract: HMC729LC3C
Contextual Info: HMC729LC3C v01.1008 26 GHz, T TYPE FLIP-FLOP HIGH SPEED LOGIC - SMT 7 Typical Applications Features The HMC729LC3C is ideal for: Supports Clock Frequencies up to 26 GHz • Serial Data Transmission up to 26 Gbps Differential & Singe-Ended Operation • High Speed Frequency Divider up to 26 GHz

T Flip-Flop

Contextual Info: HMC729LC3C v02.1208 26 GHz, T TYPE FLIP-FLOP HIGH SPEED LOGIC - SMT 7 Typical Applications Features The HMC729LC3C is ideal for: Supports Clock Frequencies up to 26 GHz • Serial Data Transmission up to 26 Gbps Differential & Singe-Ended Operation • High Speed Frequency Divider up to 26 GHz

SY100E151

Abstract: SY10E151 SY10E151JI
Contextual Info: SY10E151 SY100E151 6-BIT D REGISTER Micrel, Inc. SY10E151 SY100E151 DESCRIPTION FEATURES • 1100MHz toggle frequency ■ Extended 100E VEE range of –4.2V to –5.46V The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs,

SY100E151

Abstract: SY10E151 SY10E151JI
Contextual Info: SY10E151 SY100E151 6-BIT D REGISTER Micrel, Inc. SY10E151 SY100E151 DESCRIPTION FEATURES • 1100MHz toggle frequency ■ Extended 100E VEE range of –4.2V to –5.46V The SY10/100E151 offer 6 edge-triggered, high-speed, master-slave D-type flip-flops with differential outputs,

0608 smt resistor

Contextual Info: HMC679LC3C v01.0608 26 GHz, T FLIP-FLOP w/ RESET HIGH SPEED LOGIC - SMT 7 Typical Applications Features The HMC679LC3C is ideal for: Supports Clock Frequencies up to 26 GHz • Serial Data Transmission up to 26 Gbps Differential & Singe-Ended Operation • High Speed Frequency Divider up to 26 GHz

Contextual Info: HMC729LC3C v06.0514 HIGH SPEED LOGIC - SMT 26 GHz, T-FLIP-FLOP w/ RESET Typical Applications Features The HMC729LC3C is ideal for: Supports Clock Frequencies up to 26 GHz • Serial Data Transmission up to 26 Gbps Differential or Single-Ended Operation • High Speed Frequency Divider up to 26 GHz

EN210

Abstract: opja2 bb105 BF011 BF103 BF251 JKB10 TGB1000 BB015 EX310
Contextual Info: TGB1000 Series 0.8-|im BiCMOS Gate Arrays ¿IAR 2 9 199] RELEASE 1.0, JANUARY 1901 Very high performance 0.8-Mm EPIC BiCMOS process -Core Logic 2<input NAND gate typically switches in 130 ps intrinsic and 320 ps loaded -Flip-flop toggle frequency greater

74ls107a

Contextual Info: HD74LS107A. Dual J-K Negative-edge-triggered Flip-Flops with Clear |P IN ARRANGEMENT IBLOCK DIAGRAM ('A ) •RECOMMENDED OPERATING CONDITIONS Item Symbol Clock frequency Clock High P u lse min typ max Unit - 30 MHz 20 - - ns ■ F U N C T IO N TABLE Inputs