MPC821
Abstract: No abstract text available
Text: Communication Processor Module 16.14.19.2 ASYNC HDLC CHANNEL FRAME TRANSMISSION PROCESSING. The ASYNC HDLC controller is designed to work with a minimum amount of intervention from the CPU core. It operates in a similar fashion to the HDLC controller on the MPC821.
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MPC821.
MPC821
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hdlc
Abstract: 806C MC68360 MC68360 microcode ethernet
Text: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR Freescale Semiconductor, Inc. TECHNICAL INFORMATION Asynchronous HDLC MC68360 ASYNC HDLC Protocol Microcode User’s Manual Rev 1.1 January 24, 1996 For More Information On This Product, Go to: www.freescale.com
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MC68360
hdlc
806C
MC68360 microcode ethernet
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TCXO A31 10MHZ
Abstract: MT48LC4M32B2TG-6 L1V16 Datum OCXO
Text: PRELIMINARY PRODUCT BRIEF: SUBJECT TO CHANGE Rev: 091407 DS34S108, DS34S104, DS34S102, DS34S101 Description Abridged General Description Features The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34S108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34S108,
DS34S104,
DS34S102,
DS34S101
DS34S108
823/G
board25
DS34S108
TCXO A31 10MHZ
MT48LC4M32B2TG-6
L1V16
Datum OCXO
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RESREF
Abstract: DS34T108 MDIO MDC
Text: ABRIDGED DATA SHEET Rev: 121407 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
DS34S108,
DS34S104,
DS34S102,
DS34S101.
RESREF
MDIO MDC
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ITR17
Abstract: ITR24 80X86 AD10 AD11 AD12 AD14 ITR28
Text: 29C94 MATRA MHS Multi-Channel HDLC Protocol Controller Description The MHS 29C94 is a multi channel data link protocol controller device. It multiplexes/demultiplexes up to 32 full duplex data channels to support implementation of high speed data links based on either HDLC protocol or
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29C94
29C94
ITR17
ITR24
80X86
AD10
AD11
AD12
AD14
ITR28
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RLOF 100
Abstract: DS34t108 TDM8
Text: ABRIDGED DATA SHEET Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description 3 The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
DS34T101/DS34T102/DS34T104/DS34T108
RLOF 100
TDM8
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Ethernet to HDLC
Abstract: hdlc Ethernet to FIFO ethernet MLN7000 HDLC to Ethernet
Text: Home l Contact us l Sitemap l Korean l MLN7000 is a cost-effective single chip solution for 8-port Ethernet to HDLC High-level Data Link Control bridge. The chip for connecting Ethernet to HDLC is usually installed in various IP-based xDSL network such as ADSL, SDSL, VDSL and G.HDSL. MLN7000 has
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MLN7000
100Mbps
16bit
32way
240-pin
Ethernet to HDLC
hdlc
Ethernet to FIFO
ethernet
HDLC to Ethernet
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Untitled
Abstract: No abstract text available
Text: ABRIDGED DATA SHEET Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
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Untitled
Abstract: No abstract text available
Text: ABRIDGED DATA SHEET Rev: 040108 DS34S101//DS34S102/DS34S104/DS34S108 Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC RFC-compliant DS34S108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34S101//DS34S102/DS34S104/DS34S108
32-Bit
16-Bit
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DS34T101
Abstract: D2048 DS34S101 DS34S102 DS34T104 DS34T101GN DS34T102GN DS34T104GN DS34T108GN RFC4553
Text: ABRIDGED DATA SHEET Rev: 042608 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
preS108,
DS34S104,
DS34S102,
DS34S101.
DS34T102,
DS34T104
DS34T101
D2048
DS34S101
DS34S102
DS34T101GN
DS34T102GN
DS34T104GN
DS34T108GN
RFC4553
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DS34T104GN
Abstract: 3216 footprint IPC TDM8 DS34T101GN DS34T102GN DS34T104 DS34T108GN 7U22 DS34T10x
Text: Rev: 072707 DS34T101/DS34T102/DS34T104/DS34T108 Single/Dual/Quad/Octal TDM-Over-Packet Chip General Description 3 The IETF PWE SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34T108 allows up to eight T1/E1 links or frame-based serial HDLC links to be transported transparently through a switched IP or
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DS34T101/DS34T102/DS34T104/DS34T108
DS34T108
823/G
DS34T104GN
3216 footprint IPC
TDM8
DS34T101GN
DS34T102GN
DS34T104
DS34T108GN
7U22
DS34T10x
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MPC860
Abstract: No abstract text available
Text: 12/97 REV 0 Application Note Example Software For the MPC860 Demonstrating HDLC Operation Netcomm Applications Motorola, Austin, Texas This software demonstrates HDLC operation on the MPC860 using the SCC2 serial channel. It is a reference design that will educate you on how to initialize the MPC860
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MPC860
MPC860
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Ethernet to HDLC
Abstract: MLN7000 ethernet network switch CIRCUIT diagram DSLAM ip dslam hdlc 8 port network switch CIRCUIT diagram HDLC to Ethernet 8 port ethernet switch
Text: MLN7000 MLN7000 PRODUCT BRIEF 8-Port Frame Processor for DSLAM of the IP-Based xDSL 01 Introduction MLN7000 is a cost-effective single chip solution for 8-port Ethernet to HDLC bridge. The bridge chip for connecting Ethernet to HDLC is usually installed in various IP-based xDSL network such as ADSL, SDSL, VDSL and G.HDSL. The MLN7000 has eight Ethernet MACs that can
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MLN7000
MLN7000
100Mbps
32way
16bit
240pin
03Diagram
Ethernet to HDLC
ethernet network switch CIRCUIT diagram
DSLAM
ip dslam
hdlc
8 port network switch CIRCUIT diagram
HDLC to Ethernet
8 port ethernet switch
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AN8260
Abstract: No abstract text available
Text: FCC in HDLC Mode What you will learn • What is an FCC? • What are the FCC pins? • How an FCC operates • What is FCC parameter RAM • What is FCC protocol specific parameter RAM • How to select and configure the clocks • How an FCC transmits and receives in HDLC
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bits-24
0x1000;
0x400;
0x8000)
0xB000)
AN8260
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PQR160
Abstract: No abstract text available
Text: PRELIMINARY Am186 CH High-Performance, 80C186-Compatible 16-Bit Embedded HDLC Microcontroller DISTINCTIVE CHARACTERISTICS • E86™ family of x86 embedded processors offers improved time-to-market – Software migration backwards- and upwardscompatible
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Am186TMCH
80C186-Compatible
16-Bit
E86TM
55-ns
Am386,
Am486,
Am186,
Am188,
PQR160
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PHY registers map
Abstract: APP3488 DS33Z11 DS33Z44
Text: Maxim > App Notes > TELECOM Keywords: elite, LAN, WAN, ethernet, HDLC, EEPROM, E2PROM, SPI, hardware, app note 3449 Mar 01, 2005 APPLICATION NOTE 3488 EEPROM Programming Instructions for DS33Z11/DS33Z44 Abstract: The Dallas Semiconductor Ethernet link transport engine ELITE product line was created to bridge WAN to
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DS33Z11/DS33Z44
DS33Z11
DS33Z44,
com/an3488
DS33Z11:
DS33Z44:
AN3488,
APP3488,
Appnote3488,
PHY registers map
APP3488
DS33Z44
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DS21455
Abstract: DS21458 DS26528 DS33Z11 DS33Z41 RFC1662 G.SHDSL Industry Single-Chip 0301H 4BC20
Text: DS33Z41 Quad IMUX Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over up to four interleaved PDH/TDM data streams using robust,
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DS33Z41
DS33Z41
512Kbps.
DS21455
DS21458
DS26528
DS33Z11
RFC1662
G.SHDSL Industry Single-Chip
0301H
4BC20
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Untitled
Abstract: No abstract text available
Text: DS33Z41 Quad IMUX Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over up to four interleaved PDH/TDM data streams using robust,
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DS33Z41
DS33Z41
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BEL 100p 7D transistor datasheet
Abstract: 8155 intel microprocessor pin diagram RPC23 DS21455 DS21458 DS33Z11 DS33Z41 RFC1662 Intel 8155 Application Notes 8155 intel microprocessor block diagram
Text: DS33Z41 Quad IMUX Ethernet Mapper www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 LAPS for transmission over up to four interleaved PDH/TDM data streams using robust,
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DS33Z41
DS33Z41
BEL 100p 7D transistor datasheet
8155 intel microprocessor pin diagram
RPC23
DS21455
DS21458
DS33Z11
RFC1662
Intel 8155 Application Notes
8155 intel microprocessor block diagram
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PQR160
Abstract: No abstract text available
Text: PRELIMINARY Am186 CH High-Performance, 80C186-Compatible 16-Bit Embedded HDLC Microcontroller Back DISTINCTIVE CHARACTERISTICS • E86™ family of x86 embedded processors offers improved time-to-market – Software migration backwards- and upwardscompatible
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Am186TMCH
80C186-Compatible
16-Bit
E86TM
55-ns
Am386,
Am486,
Am186,
Am188,
PQR160
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diagram LG 21 fs 4 bg model circuits
Abstract: ABB a600 HDLC32 CMM-10 hdlc S-Class JTAG pins MC92460 MPC106 MPC8260 CRC-CCITT32
Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MC92460UM/D 5/2002 REV 2.2 MC92460 Multichannel HDLC User’s Manual For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED:
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MC92460UM/D
MC92460
diagram LG 21 fs 4 bg model circuits
ABB a600
HDLC32
CMM-10
hdlc
S-Class JTAG pins
MPC106
MPC8260
CRC-CCITT32
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e1 E2 e3 liu transceiver
Abstract: No abstract text available
Text: PRELIMINARY-SUBJECT TO CHANGE ABRIDGED DATA SHEET Rev: 091407 DS34S101//DS34S102/DS34S104/DS34S108 Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices General Description The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC draft-compliant DS34S108 allows up to eight T1/E1
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DS34S108
823/G
DS34S101/DS34S102/DS34S104/DS34S108
e1 E2 e3 liu transceiver
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CD 40818 BE
Abstract: capacitor PMR 202 DM preset 103 CD4400 ARM7 ISA RW185 40818 SPC3 st c transistor 40410 CL-CD4400s
Text: CL-CD4400 'CIRRUSIDG/C Advance Data Book FEATURES • Four full-duplex, multi-protocol serial channels ■ All channels support async-HDLC/PPP, async, HDLC, or programmable sync ■ Sync bit rates up to 8 Mbits/sec. on all channels; up to 52 Mbits/sec. on a single channel in HDLC or
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CL-CD4400
inte83
CD 40818 BE
capacitor PMR 202 DM
preset 103
CD4400
ARM7 ISA
RW185
40818
SPC3 st c
transistor 40410
CL-CD4400s
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Untitled
Abstract: No abstract text available
Text: C L -C D 4 4 0 0 Advance D a ta Book ' c ir r u s L O G IC FEATURES High-Performance Four-Channel Communications Controller • Four full-duplex, multi-protocol serial channels ■ All channels support async-HDLC/PPP, async, HDLC, or programmable sync ■ Sync bit rates up to 8 Mbits/sec. on all channels;
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