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    HCT10 Search Results

    HCT10 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CD74HCT10MT Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD54HCT109F3A Texas Instruments High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and Reset 16-CDIP -55 to 125 Visit Texas Instruments Buy
    CD54HCT10F3A Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-CDIP -55 to 125 Visit Texas Instruments Buy
    CD74HCT10M96G4 Texas Instruments High Speed CMOS Logic Triple 3-Input NAND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT109M Texas Instruments High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 Visit Texas Instruments Buy
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    HCT10 Price and Stock

    Rochester Electronics LLC 74HCT107D-Q100J

    74HCT107 - DUAL JK FLIP-FLOP WIT
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey 74HCT107D-Q100J Bulk 44,366 1,967
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    Rochester Electronics LLC CD74HCT109E

    IC FF JK TYPE DUAL 1BIT 16DIP
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    DigiKey CD74HCT109E Tube 27,587 599
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    Rochester Electronics LLC CD74HCT10M

    IC GATE NAND 3CH 3-INP 14SOIC
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    DigiKey CD74HCT10M Tube 21,437 547
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    Rochester Electronics LLC 74HCT109D,652

    IC FF JK TYPE DUAL 1BIT 16SO
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    DigiKey 74HCT109D,652 Bulk 15,650 1,410
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    Nexperia 74HCT109D,653

    IC FF JK TYPE DUAL 1BIT 16SO
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    DigiKey 74HCT109D,653 Reel 15,000 2,500
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    Avnet Americas 74HCT109D,653 Reel 8 Weeks 5,000
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    Mouser Electronics 74HCT109D,653 2,230
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    Newark 74HCT109D,653 Cut Tape 2,408 1
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    TTI 74HCT109D,653 Reel 5,000
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    Avnet Silica 74HCT109D,653 2,500 10 Weeks 2,500
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    EBV Elektronik 74HCT109D,653 2,500 10 Weeks 2,500
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    Find more HCT10 price and stock on Findchips.com

    HCT10 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    HCT10 System Logic Semiconductor Triple 3-Input NAND Gate(High-Performance Silicon-Gate CMOS) Original PDF
    HCT-100 InfraRed Associates Mercury Cadmium Telluride - HgCdTe Detectors Scan PDF

    HCT10 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    HC10

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HCT10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


    Original     		HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 HC10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 PDF

    CD74HCT107

    Abstract: CD54HC107F3A CD54HCT107F3A CD74HC107E HC107 HCT10
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139B Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised December 2002


    Original     		HC107 HCT10 CD54/74HC107, CD54/74HCT107 SCHS139B HC107 HCT107 CD74HCT107 CD54HC107F3A CD54HCT107F3A CD74HC107E HCT10 PDF

    HC-107

    Abstract: HC107
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54/74HC107, CD54/HCT107 Data sheet acquired from Harris Semiconductor SCHS139A Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2000 Features


    Original     		HC107 HCT10 CD54/74HC107, CD54/74HCT107 SCHS139A HC107 HCT107 HC-107 PDF

    KK74AC109

    Abstract: KK74AC109D KK74AC109N
    Text: TECHNICAL DATA KK74AC109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs.


    Original     		KK74AC109 KK74AC109 LS/ALS109 HC/HCT109. 012AC) KK74AC109D KK74AC109N PDF

    HC107

    Abstract: 74HCT 74LS CD74HC107 CD74HC107E CD74HCT107 CD74HCT107E HCT10
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139 Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times


    Original     		HC107 HCT10 CD74HC107, CD74HCT107 SCHS139 CD74HC107 CD74HCT107 HC107 74HCT 74LS CD74HC107E CD74HCT107E HCT10 PDF

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


    Original     		CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 HCT10 PDF

    HCT10

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


    Original     		HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74HC/HCT107 flip-flops D U A L JK FLIP-F LO P W ITH R E SE T ; N E G A T IV E -E D G E T R IG G E R FEATURES T Y P IC A L • Output capability: standard • I q q category: flip-flops SYM BO L T h e reset {n R is an asy n ch ron ou s active L O W input. W hen L O W , it overrides the


    OCR Scan     		74HC/HCT107 PDF

    CD54HC107

    Abstract: CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HC107 HCT10
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


    Original     		HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M HCT10 PDF

    CD54HC10

    Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


    Original     		HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 PDF

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


    Original     		CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 HC/HCT73 PDF

    IN74ACT109D

    Abstract: IN74ACT109N
    Text: IN74ACT109 DUAL J-K FLIP-FLOP WITH SET AND RESET High-Speed Silicon-Gate CMOS • • • • The IN74ACT109 is identical in pinout to the LS/ALS109, HC/HCT109. The IN74ACT109 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.


    Original     		IN74ACT109 IN74ACT109 LS/ALS109, HC/HCT109. IN74ACT109D IN74ACT109N PDF

    HC-86

    Abstract: HC09 hcoo HC07 hc86 hc132 HC123A HC-107 HC251 HC4050
    Text: SELECTION GUIDE FUNCTION GATE BUFFER FLIP-FLOP STANDARD CODE NAND HCOO, HCTOO, HC03, HC10, HCT10, HC20, HC30, HC133, HCT30 NOR HC02, HCT02, HC27, HCT27, HC4002, HC4078 AND HC08, HCT08, HC09, HC11, HC21 OR HC32, HCT32, HC4072, HC4075 EX NOR HC266, HC7266 EX OR


    OCR Scan     		HCT10, HC133, HCT30 HCT02, HCT27, HC4002, HC4078 HCT08, HCT32, HC4072, HC-86 HC09 hcoo HC07 hc86 hc132 HC123A HC-107 HC251 HC4050 PDF

    IN74AC109

    Abstract: IN74AC109D IN74AC109N
    Text: TECHNICAL DATA IN74AC109 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible


    Original     		IN74AC109 LS/ALS109 HC/HCT109. IN74AC109 IN74AC109D IN74AC109N PDF

    IN74AC10N

    Abstract: IN74AC10D
    Text: TECHNICAL DATA IN74AC10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The IN74AC10 is identical in pinout to the LS/ALS10, HC/HCT10. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS


    Original     		IN74AC10 IN74AC10 LS/ALS10, HC/HCT10. IN74AC10N IN74AC10D PDF

    Untitled

    Abstract: No abstract text available
    Text: Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES DESCRIPTION • Wide supply voltage range of 1.2 to 3.6 V The 74LVC1G9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109.


    OCR Scan     		74LVC109 74LVC1G9 74HC/HCT109. 74LVC109 SV00904 PDF

    "J-K Flip flop"

    Abstract: CD54HC107F3A HC107 T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


    Original     		HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 "J-K Flip flop" CD54HC107F3A T flip flop IC CD54HC107 CD74HC107 CD74HC107E CD74HC107M HCT10 PDF

    74HC/HCT/HCU/HCMOS Logic Family Specifications

    Abstract: 74HC/HCT/HCU/HCMOS Logic Package Information 74HC/HCT/HCU/HCMOS Logic Package Outlines IC06 74HC/HCT/HCU/HCMOS Logic Package Information Package Information philips IC06 74HC Logic Family Specifications logic family specification philips ic06 HCT10 IC06 74HC/HCT/HCU/HCMOS Logic Package Outline The IC06 74HC/HCT/HCU/HCMOS Logic Package
    Text: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT10


    Original     		74HC/HCT/HCU/HCMOS 74HC/HCT10 74HC/HCT10 74HCT 74HC/HCT/HCU/HCMOS Logic Family Specifications 74HC/HCT/HCU/HCMOS Logic Package Information 74HC/HCT/HCU/HCMOS Logic Package Outlines IC06 74HC/HCT/HCU/HCMOS Logic Package Information Package Information philips IC06 74HC Logic Family Specifications logic family specification philips ic06 HCT10 IC06 74HC/HCT/HCU/HCMOS Logic Package Outline The IC06 74HC/HCT/HCU/HCMOS Logic Package PDF

    HC107

    Abstract: CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M CD74HCT107 HCT10
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139C Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised May 2003


    Original     		HC107 HCT10 CD54HC107, CD74HC107, CD74HCT107 SCHS139C HC107 CD74HCT107 CD54HC107 CD54HC107F3A CD74HC107 CD74HC107E CD74HC107M HCT10 PDF

    CD54HC10

    Abstract: CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 HCT10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


    Original     		HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128B HCT10 CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HC10E CD74HCT10 HC10 PDF

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74 HC107 , CD74 HCT10 7 /Subject (Dual J-K FlipFlop with Reset Negative- CD54HC107, CD74HC107, HCT107 Data sheet acquired from Harris Semiconductor SCHS139D Dual J-K Flip-Flop with Reset Negative-Edge Trigger March 1998 - Revised October 2003


    Original     		CD54HC107, CD74HC107, CD74HCT107 SCHS139D HC107 CD74HCT107 HC/HCT73 PDF

    74hct10

    Abstract: 74HC10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54/74HC10, CD54/HCT10 Data sheet acquired from Harris Semiconductor


    Original     		CD54/74HC10, CD54/74HCT10 SCHS128A HCT10 HCT10 SDYA012 SN54/74HCT SCLA011 SCLA008 SZZU001B, 74hct10 74HC10 PDF

    KK74ACT10

    Abstract: KK74ACT10D KK74ACT10N
    Text: TECHNICAL DATA KK74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The KK74ACT10 is identical in pinout to the LS/ALS10, HC/HCT10. The KK74ACT10 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. • TTL/NMOS Compatible Input Levels


    Original     		KK74ACT10 KK74ACT10 LS/ALS10, HC/HCT10. KK74ACT10N KK74ACT10D 012AB) PDF

    CD74HC10E

    Abstract: CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 HCT10
    Text: [ /Title CD74 HC10, CD74 HCT10 /Subject (High Speed CMOS Logic Triple 3-Input NAND Gate) /Autho r () /Keywords (High Speed CMOS Logic Triple 3-Input NAND Gate, High Speed CMOS Logic Triple 3-Input NAND Gate, Harris Semi- CD54HC10, CD74HC10, HCT10, HCT10


    Original     		HCT10 CD54HC10, CD74HC10, CD54HCT10, CD74HCT10 SCHS128C HCT10 CD74HC10E CD54HC10 CD54HC10F3A CD54HCT10 CD54HCT10F3A CD74HC10 CD74HCT10 HC10 PDF