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    H64 PACKAGE Search Results

    H64 PACKAGE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TPH9R00CQH Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation
    TPH2R408QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 120 A, 0.00243 Ohm@10V, SOP Advance Visit Toshiba Electronic Devices & Storage Corporation
    XPH2R106NC Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 110 A, 0.0021 Ω@10V, SOP Advance(WF) Visit Toshiba Electronic Devices & Storage Corporation
    XPH3R206NC Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 70 A, 0.0032 Ω@10V, SOP Advance(WF) Visit Toshiba Electronic Devices & Storage Corporation
    TPH4R008QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 86 A, 0.004 Ohm@10V, SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation

    H64 PACKAGE Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    H64 Package Cypress Semiconductor Ceramic Windowed J-Leaded Chip Carriers Original PDF

    H64 PACKAGE Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: Package Diagrams Ceramic Windowed J-Leaded Chip Carriers 32-Pin Windowed Leaded Chip Carrier H32 1 Package Diagrams 28-Pin Windowed Leaded Chip Carrier H64 51-80077 2 Package Diagrams 32-Pin Windowed Leaded Chip Carrier H65 51-80078 3 Package Diagrams 44-Pin Windowed Leaded Chip Carrier H67


    Original
    32-Pin 28-Pin 44-Pin 68-Pin 84-Leaded PDF

    80081

    Abstract: H65 Package
    Text: Package Diagram Ceramic Windowed J-Leaded Chip Carriers 32-Pin Windowed Leaded Chip Carrier H32 1 Package Diagram 28-Pin Windowed Leaded Chip Carrier H64 51-80077 2 Package Diagram 32-Pin Windowed Leaded Chip Carrier H65 51-80078 3 Package Diagram 44-Pin Windowed Leaded Chip Carrier H67


    Original
    32-Pin 28-Pin 44-Pin 68-Pin 84-Leaded 80081 H65 Package PDF

    H641

    Abstract: 005 05 H64-1
    Text: PACKAGE INFORMATION Micrel 64 LEAD EPAD-TQFP DIE UP (H64-1) +0.05 –0.05 +0.002 –0.002 +0.05 –0.05 +0.012 –0.012 +0.03 –0.03 +0.012 –0.012 +0.15 –0.15 +0.006 –0.006 +0.05 –0.05 +0.002 –0.002 Rev. 02 Rev.: B 1 Amendment: 0 Issue Date: March 2000


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    H64-1) H641 005 05 H64-1 PDF

    28-pin

    Abstract: carrier H84 Package 68-pin circuit diagram diagram free transistor equivalent book H67 Package led data book free download h846
    Text: Package Diagram Ceramic Windowed J-Leaded Chip Carriers 32-Pin Windowed Leaded Chip Carrier H32 1 Package Diagram 28-Pin Windowed Leaded Chip Carrier H64 2 Package Diagram 32-Pin Windowed Leaded Chip Carrier H65 3 Package Diagram 44-Pin Windowed Leaded Chip Carrier H67


    Original
    32-Pin 28-Pin 44-Pin 68-Pin 84-Lead carrier H84 Package circuit diagram diagram free transistor equivalent book H67 Package led data book free download h846 PDF

    7C335

    Abstract: C3355 CY7C335 7c332 83HM
    Text: 7c335: 7/16/91 Revision: Thursday, January 13, 1994 CY7C335 Universal Synchronous EPLD Features D 100ĆMHz output registered operation D Twelve I/O macrocells, each having: Ċ Registered, threeĆstate I/O pins Ċ Input and output register clock seĆ lect multiplexer


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    7c335: CY7C335 14-controlled) terms32 100MHz CY7C335, 7C335 C3355 CY7C335 7c332 83HM PDF

    cy7c344b-25hmb

    Abstract: 10HC 74HC 7C344 C344 CY7C344 CY7C344B
    Text: fax id: 6101 1CY 7C34 4B CY7C344 CY7C344B 32-Macrocell MAX EPLD Features sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an


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    CY7C344 CY7C344B 32-Macrocell CY7C344 cy7c344b-25hmb 10HC 74HC 7C344 C344 CY7C344B PDF

    C344

    Abstract: 10HC 74HC 7C344 CY7C344 CY7C344B 7C344-25 TEA16
    Text: fax id: 6101 1CY 7C34 4B CY7C344 CY7C344B 32-Macrocell MAX EPLD Features sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an


    Original
    CY7C344 CY7C344B 32-Macrocell CY7C344 C344 10HC 74HC 7C344 CY7C344B 7C344-25 TEA16 PDF

    diode C522

    Abstract: C525 DIODE C524 DIODE diode C521 C521 DIODE ST DIODE C522
    Text: ¡nterrratinnal ^ or R ectifier pd-9.h64 IRGNIN075M12 "CHOPPER HIGH SIDE SWITCH' IGBTINT-A-PAK Low conduction loss IGBT High Side Switch 03 V CE= 1200V lc = 7 5 A -0 1 «Rugged Design •Simple gate-drive •Switching-Loss Rating includes all "tail"


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    IRGNIN075M12 100nH C-526 diode C522 C525 DIODE C524 DIODE diode C521 C521 DIODE ST DIODE C522 PDF

    Untitled

    Abstract: No abstract text available
    Text: MbE T> m CONNOR — ÜJINFIELD CORP 2343431 0000331 b HCNül AURORA. CONNOR-WINFIELD CORPORATION T-50-23 IL. 60505 PHONE 708 851-4722 FAX (708) 851-5040 8 PIN DIP HCMOS H54 SPECIFICATIONS H64 Frequency Range Frequency 250Hz Tolerance Temperature to 6 0 M H z


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    53M3M31 T-50-23 250Hz 60MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: U631 H64 Software Controlled 8Kx8 nvSRAM □ Packages: P D IP 28 300 mil S O P28 (330 mil) Features □ H igh-perform ance C M O S non­ volatile static RAM 8192 x 8 bits □ 25, 35 and 45 ns Access Tim es □ 12, 20 and 25 ns O utput Enable A ccess T im es


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    PDF

    PACKAGE DIMENSIONS CASE 751-03

    Abstract: MB87001 ADI1763 MC12034A MC12034B MB87001A
    Text: Order this data sheet by MC12034A/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC12034A MC12034B 2.0 GHz -32/-33/-h64/-65 Low-Power Two-Modulus Prescaler T he M C 1 20 34A can be used w ith C M O S syn th e size rs requiring po sitive ed ge s to trig ­ g e r internal cou nters such as M o to ro la ’s M C 1 45 xxx series in a PLL to provide tuning


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    MC12034A/D -32/-33/-h64/-65 MC12034A MC145xxx MC12034B MB87001. O2465 MC12034A PACKAGE DIMENSIONS CASE 751-03 MB87001 ADI1763 MB87001A PDF

    c677

    Abstract: No abstract text available
    Text: I U J O J . / / 1 0 /9 1 Revision: Friday, March 2 6 ,1993b M fP ? 1993 CY7C335 7J s CYPRESS SEMICONDUCTOR Universal Synchronous EPLD construct very high performance state ma­ chines. The architecture of the CY7C335, consist­ ing of the user-configurable output macrocell, bidirectional I/O capability, input reg­


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    1993b CY7C335 CY7C335, CY7C335-50JC CY7C335-50PC CY7C335-50WC CY7C335-40WI CY7C335-83PC CY7C335-40PI CY7C335-83JC c677 PDF

    TCO - 909 F 10 MHz

    Abstract: TCO - 909 C335 CY7C335 TCO - 909 F C335A
    Text: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer


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    CY7C335 100-MHz CY7C335â 28-Lead 300-Mil) 40DMB TCO - 909 F 10 MHz TCO - 909 C335 TCO - 909 F C335A PDF

    I8272

    Abstract: 20RA10 20RA10-15 PLDC20RA10 HP 2502 470S3 HP 2502 8 pin PLDC20RA10-30WC
    Text: CYPRESS 4bE SEMICONDUCTOR SSfl^tiba D -i*\ -O c\ 'TH □ OÜb'îSM G E3CYP PLDC20RA10 CYPRESS . .— — Features Advanced-user programmable macro* cell CMOS EPROM technology for repro­ grammability Up to 20 Input terms 10 programmable I/O macrocells Output macrocell programmable as


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    PLDC20RA10 T-46-19-09 PLDC20RA10-35DI PLDC20RA10â PLDC20RA10-35PI PLDC20RA10-35DMB PLDC20RA10-35HMB PLDC20RA10-35LMB I8272 20RA10 20RA10-15 PLDC20RA10 HP 2502 470S3 HP 2502 8 pin PLDC20RA10-30WC PDF

    CY7C335-50WMB

    Abstract: C3359
    Text: = # CY7C335 C YPRESS Universal Synchronous EPLD Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer


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    14-controlled) terms--32 10-ns 28-pin, 300-mil CY7C335 100-MHz 28-Lead 300-Mil) 28-Pin CY7C335-50WMB C3359 PDF

    TCO - 909 F 10 MHz

    Abstract: TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335
    Text: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer


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    CY7C335 100-MHz 300-Mil) CY7C335â 40DMB 28-Lead 40HMB 28-Pin TCO - 909 F 10 MHz TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335 PDF

    22V10

    Abstract: 22V10-25HMB cypress 22V10 PALC22V10-25WC palc22v10-25
    Text: PAL C 22V10B/PAL C 22V10 CYPRESS SEMICONDUCTOR Reprogrammable CMOS PAL Device Features • Advanced second generation PAL architecture • Low power — 55 mA max “L” — 90 mA max standard — 120 mA max military • CMOS EPR O M technology for reprogrammability


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    22V10B/PAL 22V10 38-00020-E 22V10 22V10-25HMB cypress 22V10 PALC22V10-25WC palc22v10-25 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C335 PRELIMINARY CYPRESS SEMICONDUCTOR Features • 83-MHz registered pipelined operation • Ttoelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer


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    CY7C335 83-MHz SC335-66H CY7C335-66PI CY7C335-- 66DMB CY7C335-66HM CY7C335-66LM CY7C335 PDF

    7C332

    Abstract: No abstract text available
    Text: CY7C335 Universal Synchronous EPLD V CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer


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    100-MHz CY7C335 cl300-Mil) 28-Pin 28-Lead 300-Mil) 7C332 PDF

    Untitled

    Abstract: No abstract text available
    Text: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan­ dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output


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    PLDC20G10B/PLDC20G10 24-Pin 20L10, 12L10 CG7C323 PLD20G10 28-pin 00019-F PDF

    12L10

    Abstract: PLD20G 20G10B-20 16L6 18L4 20L10 20L8 CG7C323B-A15HC J-64
    Text: C Y P R ES S SEMI CONDUCTOR 4bE T> 2 5 0 ^ 2 QQOb^ab T QCYP PLDC20G10B/PLDC20G10 ir - - - ~— CMOS Generic 2 4 ^ n Reprogrammable Logic Device SEMICONDUCTOR Features • Fast — Commercial: tpo = IS ns, tco = 1 ns, ts = 12 ns — Military: tpo = 20 ns, tco ~ 15 os,


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    PLDC20G10B/PLDC20G10 24-Pin 20L10, 12L10 PLDC20G10-35HC CG7C323â A35JC/JS12! CG7C323-A35HC PLDC20G10-40DMB PLDC20G10-40LMB PLD20G 20G10B-20 16L6 18L4 20L10 20L8 CG7C323B-A15HC J-64 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C344 CY7C344B y CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins


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    CY7C344 CY7C344B 32-Macrocell CY7C344/CY7C344B PDF

    74HC

    Abstract: 7C344 CY7C344 CY7C344B 20C02 DD131
    Text: CY7C344 CY7C344B *0 CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins


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    CY7C344 CY7C344B 32-Macrocell CY7C344) 65-micron CY7C344B) 28-pin 300-mil 74HC 7C344 20C02 DD131 PDF

    Untitled

    Abstract: No abstract text available
    Text: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin


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    28-pin 28-pin termW22 28-Lead 300-Mil) CY7C331 001305b PDF