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    H510 Price and Stock

    Murata Manufacturing Co Ltd GRM0335C1H510GA01D

    CAP CER 51PF 50V C0G/NP0 0201
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    DigiKey GRM0335C1H510GA01D Digi-Reel 99,331 1
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    GRM0335C1H510GA01D Cut Tape 99,331 1
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    GRM0335C1H510GA01D Reel 90,000 15,000
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    TDK Electronics B32714H5106K000

    MKP DC FILTERING - 500VDC, 10UF
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    DigiKey B32714H5106K000 Bulk 1,552 1
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    NXP Semiconductors NXH5104UK-A1Z

    IC EEPROM 4MBIT SPI 13WLCSP
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    DigiKey NXH5104UK-A1Z Digi-Reel 1,530 1
    • 1 $8.65
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    NXH5104UK-A1Z Cut Tape 1,530 1
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    NXP Semiconductors NXQ1TXH5-101J

    RF XMITTER 110-205KHZ 32VFQFN
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    DigiKey NXQ1TXH5-101J Cut Tape 1,487 1
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    • 100 $4.1863
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    Murata Manufacturing Co Ltd DLW32SH510XF2L

    CMC 51UH 200MA 2LN SMD AEC-Q200
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    DigiKey DLW32SH510XF2L Digi-Reel 623 1
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    • 1000 $0.72156
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    DLW32SH510XF2L Cut Tape 623 1
    • 1 $1.43
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    H510 Datasheets (19)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    H5100 Leader Electronic Relative Humidity Sensor Original PDF
    H51000500000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 7.62MM Original PDF
    H51000510000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 7.62MM Original PDF
    H51000520000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 7.62MM Original PDF
    H51010500000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 3.5MM Original PDF
    H51010510000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 3.5MM Original PDF
    H51010520000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 3.5MM Original PDF
    H51030500000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 3.81MM Original PDF
    H51030510000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 3.81MM Original PDF
    H51030520000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 3.81MM Original PDF
    H51050500000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 5.08MM Original PDF
    H51050510000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 5.08MM Original PDF
    H51050520000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 5.08MM Original PDF
    H51070500000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 5MM Original PDF
    H51070510000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 5MM Original PDF
    H51070520000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 5MM Original PDF
    H510A0500000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 7.5MM Original PDF
    H510A0510000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 7.5MM Original PDF
    H510A0520000G Amphenol Anytek Connectors, Interconnects - Terminal Blocks - Headers, Plugs and Sockets - TERM BLOCK PLUG 10POS STR 7.5MM Original PDF

    H510 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    HC1S60

    Abstract: HC1S40F780 Altera Stratix V
    Text: 1. Introduction to HardCopy Stratix Devices H51001-2.4 Introduction HardCopy Stratix ® structured ASICs, Altera’s second-generation HardCopy structured ASICs, are low-cost, high-performance devices with the same architecture as the high-density Stratix FPGAs. The


    Original     		H51001-2 Stratix841 HC1S60 HC1S40F780 Altera Stratix V PDF

    verilog code power gating

    Abstract: led clock circuit diagram Pulse generator circuit verilog code for combinational loop digital led clock circuit diagram vhdl code for combinational circuit
    Text: 19. Design Guidelines for HardCopy Series Devices H51011-3.3 Introduction HardCopy series devices provide dramatic cost savings, performance improvement, and reduced power consumption over their programmable counterparts. In order to ensure the smoothest possible


    Original     		H51011-3 verilog code power gating led clock circuit diagram Pulse generator circuit verilog code for combinational loop digital led clock circuit diagram vhdl code for combinational circuit PDF

    HC210

    Abstract: AND214 HC220 HC230 HC240 SSTL-18
    Text: 4. DC and Switching Specifications and Operating Conditions H51018-3.1 Introduction This chapter provides preliminary information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for HardCopy II devices.


    Original     		H51018-3 HC210 AND214 HC220 HC230 HC240 SSTL-18 PDF

    HC230F1020

    Abstract: encounter conformal equivalence check user guide AN432 EP2S130F1020C4 HC240 EP2S180F1020
    Text: 5. Quartus II Support for HardCopy II Devices H51022-2.4 HardCopy II Device Support Altera HardCopy® II devices feature 1.2-V, 90 nm process technology, and provide a structured ASIC alternative to increasingly expensive multi-million gate ASIC designs. The HardCopy II design methodology


    Original     		H51022-2 HC230F1020 encounter conformal equivalence check user guide AN432 EP2S130F1020C4 HC240 EP2S180F1020 PDF

    HC1S60

    Abstract: interface. jp.co
    Text: 11. Boundary-Scan Support H51004-3.3 IEEE Std. 1149.1 JTAG Boundary-Scan Support All HardCopy Stratix® structured ASICs provide JTAG boundry-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-1990 specification. The BST architecture offers the capability to efficiently test


    Original     		H51004-3 HC1S60 interface. jp.co PDF

    HC1S40

    Abstract: HC1S60
    Text: 10. Description, Architecture, and Features H51002-3.3 Introduction HardCopy Stratix® structured ASICs provide a comprehensive alternative to ASICs. The HardCopy Stratix device family is fully supported by the Quartus® II design software, and, combined with a vast


    Original     		H51002-3 HC1S40 HC1S60 PDF

    Untitled

    Abstract: No abstract text available
    Text: 21. Back-End Design Flow for HardCopy Series Devices H51019-1.3 Introduction This chapter discusses the back-end design flow executed by the HardCopy Design Center when developing your HardCopy series device. The chapter is divided into two sections: •


    Original     		H51019-1 PDF

    encounter conformal equivalence check user guide

    Abstract: AN432 EP2S130F1020C4 HC230F1020 HC240
    Text: 5. Quartus II Support for HardCopy II Devices H51022-2.5 HardCopy II Device Support Altera HardCopy® II devices feature 1.2-V, 90 nm process technology, and provide a structured ASIC alternative to increasingly expensive multi-million gate ASIC designs. The HardCopy II design methodology


    Original     		H51022-2 encounter conformal equivalence check user guide AN432 EP2S130F1020C4 HC230F1020 HC240 PDF

    HC20K1000

    Abstract: HC20K1500 HC20K400 HC20K600 jtag timing
    Text: 9. Boundary-Scan Support H51009-2.3 IEEE Std. 1149.1 JTAG Boundary-Scan Support All HardCopy devices provide JTAG boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-1990 specification. HardCopy APEX devices support the JTAG instructions shown in Table 9–1.


    Original     		H51009-2 HC20K1000 HC20K1500 HC20K400 HC20K600 jtag timing PDF

    TCL SERVICE MANUAL

    Abstract: EP2S60F484C4 ep2s30f484i4 EP2S60F672I4 EP2S60F484C4 pinout EP2S90F1020C5 EP2S60F484C5 EP2S180F1508I4 line interactive ups design EP2S30F484C3
    Text: 6. Script-Based Design for HardCopy II Devices H51025-1.3 Introduction The Quartus II software includes a set of command-line executables, many of which support an interactive Tcl shell. Using the Tcl shell, you can perform FPGA or HardCopy ® design operations without using the


    Original     		H51025-1 TCL SERVICE MANUAL EP2S60F484C4 ep2s30f484i4 EP2S60F672I4 EP2S60F484C4 pinout EP2S90F1020C5 EP2S60F484C5 EP2S180F1508I4 line interactive ups design EP2S30F484C3 PDF

    HC1S60

    Abstract: No abstract text available
    Text: 2. Description, Architecture, and Features H51002-3.4 Introduction HardCopy Stratix ® structured ASICs provide a comprehensive alternative to ASICs. The HardCopy Stratix device family is fully supported by the Quartus® II design software, and, combined with a vast


    Original     		H51002-3 HC1S60 PDF

    clock tree guidelines

    Abstract: No abstract text available
    Text: 7. Timing Constraints for HardCopy II Devices H51028-2.1 Introduction In a Stratix II FPGA design, a complete and accurate set of timing constraints is often not critical to achieving a fully functioning product. The reconfigurability of the FPGA means that if a timing-related problem


    Original     		H51028-2 clock tree guidelines PDF

    HC220

    Abstract: HC210 EP2S180 EP2S30 EP2S60 EP2S90 HC230 HC240 instant-on-after-50-ms
    Text: 1. Introduction to HardCopy II Devices H51015-2.5 Introduction HardCopy II devices are low-cost, high-performance structured ASICs with pin-outs, densities, and architecture that complement Stratix ® II devices. HardCopy II device features, such as phase-locked loops PLLs ,


    Original     		H51015-2 HC220 HC210 EP2S180 EP2S30 EP2S60 EP2S90 HC230 HC240 instant-on-after-50-ms PDF

    HC210

    Abstract: HC220 HC230 HC240 h jtag
    Text: 3. Boundary-Scan Support H51017-2.3 IEEE Std. 1149.1 JTAG Boundary-Scan Support All HardCopy II structured ASICs provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-1990 specification. The BST architecture offers the capability


    Original     		H51017-2 HC210 HC220 HC230 HC240 h jtag PDF

    B39191-B5026-H510

    Abstract: B5026 S6001
    Text: SAW Components SAW IF Filter W-CDMA base station, Rx Series/Type: Ordering code: B5026 B39191-B5026-H510 Date: Version: Jun 06, 2006 2.1  EPCOS AG 2005. Reproduction, publication and dissemination of this data sheet, enclosures hereto and the information contained therein without EPCOS’ prior express consent is prohibited.


    Original     		B5026 B39191-B5026-H510 DCC12A B39191-B5026-H510 B5026 S6001 PDF

    "Content Addressable Memory"

    Abstract: HC20K1000 HC20K1500 HC20K400 HC20K600
    Text: 7. Introduction to HardCopy APEX Devices H51006-2.3 Introduction HardCopy APEXTM devices enable high-density APEX 20KE device technology to be used in high-volume applications where significant cost reduction is desired. HardCopy APEX devices are physically and


    Original     		H51006-2 "Content Addressable Memory" HC20K1000 HC20K1500 HC20K400 HC20K600 PDF

    Testability

    Abstract: No abstract text available
    Text: 3. Back-End Design Flow for HardCopy Series Devices H51019-1.4 Introduction This chapter discusses the back-end design flow executed by the HardCopy Design Center when developing your HardCopy series device. The chapter is divided into two sections: •


    Original     		H51019-1 Testability PDF

    HC210

    Abstract: HC220 HC230 HC240 h jtag jtag timing
    Text: 3. Boundary-Scan Support H51017-2.4 IEEE Std. 1149.1 JTAG Boundary-Scan Support All HardCopy II structured ASICs provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1-1990 specification. The BST architecture offers the capability


    Original     		H51017-2 HC210 HC220 HC230 HC240 h jtag jtag timing PDF

    74HC230

    Abstract: HC210 BGA-614 EP2S180 EP2S30 EP2S60 EP2S90 HC220 HC230 HC240
    Text: 8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.4 Introduction Altera HardCopy® II devices and Stratix® II devices are both manufactured on a 1.2-V, 90-nm process technology and offer many similar features. Designers can use the Quartus® II software to migrate


    Original     		H51024-1 90-nm 74HC230 HC210 BGA-614 EP2S180 EP2S30 EP2S60 EP2S90 HC220 HC230 HC240 PDF

    EPCOS 800

    Abstract: SAW IF Filter EPCOS ec 600
    Text: SAW Components SAW IF filter GSM base station Series/type: Ordering code: B5045 B39201-B5045-H510 Date: Version: January 12, 2009 2.0  EPCOS AG 2009. Reproduction, publication and dissemination of this data sheet, enclosures hereto and the information contained therein without EPCOS’ prior express consent is prohibited.


    Original     		B5045 B39201-B5045-H510 DCC12A EPCOS 800 SAW IF Filter EPCOS ec 600 PDF

    digital clock project

    Abstract: HC1S60F1020 digital clock project report to download sample project of digital signal processing digital clock project report fpga altera hc1S25F672 HC1S80F1020 digital clock project program electronic code lock project
    Text: 5. Quartus II Support for HardCopy Stratix Devices H51014-3.4 Introduction Altera HardCopy devices provide a comprehensive alternative to ASICs. HardCopy structured ASICs offer a complete solution from prototype to high-volume production, and maintain the powerful


    Original     		H51014-3 digital clock project HC1S60F1020 digital clock project report to download sample project of digital signal processing digital clock project report fpga altera hc1S25F672 HC1S80F1020 digital clock project program electronic code lock project PDF

    EPC16

    Abstract: HC1S60
    Text: 12. Power-Up Modes and Configuration Emulation in HardCopy Series Devices H51012-2.5 Introduction Configuring an FPGA is the process of loading the design data into the device. Altera’s SRAM-based Stratix II, Stratix, APEX 20KC, and APEX 20KE FPGAs require configuration each time the device is


    Original     		H51012-2 EPC16 HC1S60 PDF

    HC1S80F1020

    Abstract: digital clock project report HC1S60F1020 sample project of digital signal processing digital clock project program H51014-3 HC1S40F780
    Text: 13. Quartus II Support for HardCopy Stratix Devices H51014-3.3 Introduction Altera HardCopy devices provide a comprehensive alternative to ASICs. HardCopy structured ASICs offer a complete solution from prototype to high-volume production, and maintain the powerful


    Original     		H51014-3 HC1S80F1020 digital clock project report HC1S60F1020 sample project of digital signal processing digital clock project program HC1S40F780 PDF

    EP2S60F672I4

    Abstract: EP2S30F484I4 DDR2 SDRAM sstl_18 EP2S180F1020C3 EP2S30F484C3 EP2S30F484C4 EP2S30F484C5 EP2S60F484C3 EP2S60F484C4 EP2S60F484C5
    Text: 6. Script-Based Design for HardCopy II Devices H51025-1.2 Introduction The Quartus II software includes a set of command-line executables, many of which support an interactive Tcl shell. Using the Tcl shell, you can perform FPGA or HardCopy ® design operations without using the


    Original     		H51025-1 EP2S60F672I4 EP2S30F484I4 DDR2 SDRAM sstl_18 EP2S180F1020C3 EP2S30F484C3 EP2S30F484C4 EP2S30F484C5 EP2S60F484C3 EP2S60F484C4 EP2S60F484C5 PDF