GX 717 Search Results

circuit diagram of inverting adder

Abstract: KR 108 6621 3.3V
Contextual Info: Stratix GX FPGA Family Data Sheet December 2004, ver. 2.2 Introduction The Stratix GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

EP1SGX25CF672C7

Contextual Info: Stratix GX FPGA Family Data Sheet February 2004, ver. 2.1 Introduction The Stratix GX family of devices is Altera's second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

Contextual Info: Stratix GX FPGA Family Data Sheet February 2004, ver. 2.1 Introduction The Stratix GX family of devices is Altera's second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

EP1SGX25CF672C6N

Abstract: EP1SGX40GF1020C6N EP1SGX25CF672C7 EP1SGX25CF672I6N Z0 607 MA GX 652
Contextual Info: Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions,

Contextual Info: Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions,

pseudo-random noise generator

Abstract: MAX4967 ENa 441 144bits Z0 607 MA GX 652 inter clock skew altera
Contextual Info: Section I. Stratix GX Device Family Data Sheet This section provides the data sheet specifications for Stratix GX devices. It contains feature definitions of the internal architecture, configuration information, testing information, DC operating conditions,

verilog code for 4 bit ripple COUNTER

Abstract: Quartus II Handbook version 9.1 image processing
Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing

a 1757 transistor

Abstract: Cyclone II FPGA vhdl code for asynchronous fifo TH 2028 3414 TRANSISTOR
Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing

transistor gx 734

Abstract: 1451 encoder bst 1046 Crossbar Switches SONET SDH vhdl code for 16 prbs generator din 2768 rx2 1107 MA1567
Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing

EP2SGX60EF1152C4N

Abstract: equivalent transistor K 3562 EP2SGX60DF780I4N EP2SGX60EF1152C5 EP2SGX60DF780I4 EP2SGX60DF780C5 HD-SDI serializer EP2SGX60EF1152I4N EP2SGX130GF1508C5
Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing

HSTL standards

Abstract: 15-V AGX52008-1 APEX20KC SSTL-18
Contextual Info: Section IV. I/O Standards This section provides information on Arria GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 8, Selectable I/O Standards in Arria GX Devices

6A91

Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing

15-V

Abstract: AGX52008-1 APEX20KC SSTL-18 Teradyne connector 72 pin
Contextual Info: Section IV. I/O Standards This section provides information on Arria GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 8, Selectable I/O Standards in Arria GX Devices

transistor gx 734

Abstract: HD-SDI serializer 16 bit parallel GX 6107
Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing

Contextual Info: Stratix GX November 2003, ver. 2.0 Introduction Preliminary Information Features. Altera Corporation DS-STXGX-2.0 L01-09828-00 FPGA Family Data Sheet The Stratix GX family of devices is Altera's® second FPGA family to combine high-speed serial transceivers with a scalable, high-performance

Contextual Info: Stratix GX November 2003, ver. 2.0 Introduction Preliminary Information Features. Altera Corporation DS-STXGX-2.0 FPGA Family Data Sheet The Stratix GX family of devices is Altera's® second FPGA family to combine high-speed serial transceivers with a scalable, high-performance

oc-192 serdes

Abstract: history of automatic phase selector TRANSISTOR D123 JC42 P802 SSTL-18 Compact PCI Backplane Block Diagram Altera source-synchronous
Contextual Info: Section IV. I/O Standards This section provides information about the I/O standards and interfaces for Stratix and Stratix GX devices. This section includes the following chapters: Revision History • Chapter 16, Selectable I/O Standards in Stratix & Stratix GX Devices

Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration and JTAG boundaryscan testing information, DC operating conditions, AC timing

interfacing differential logic families 1998

Abstract: 15-V SSTL-18 HSTL standards
Contextual Info: Section IV. I/O Standards This section provides information on Stratix II GX single-ended, voltage-referenced, and differential I/O standards. This section contains the following chapters: Revision History Altera Corporation • Chapter 10, Selectable I/O Standards in Stratix II & Stratix II GX

MAX4967

Abstract: 10-Gigabit EP1SGX25CF672C7
Contextual Info: Stratix GX November 2003, ver. 2.0 Introduction Preliminary Information Features. Altera Corporation DS-STXGX-2.0 L01-09828-00 FPGA Family Data Sheet The Stratix GX family of devices is Altera's® second FPGA family to combine high-speed serial transceivers with a scalable, high-performance

free verilog code of prbs pattern generator

Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing

verilog code of prbs pattern generator

Abstract: transistor gx 734 EP2SGX130
Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing

8th class date sheet 2012

Abstract: date sheet 8th class 2012 2322 640 5 bst 1046 DN 2530 ITS DRIVER CIRCUIT vhdl code for pn sequence generator MA1567
Contextual Info: Section I. Stratix II GX Device Data Sheet This section provides designers with the data sheet specifications for Stratix II GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing

AGX52009-1

Abstract: SSTL-18 XXXX7654
Contextual Info: 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices AGX52009-1.01 Introduction The Arria GX device family offers up to 840-Mbps differential I/O capabilities to support source-synchronous communication protocols such as HyperTransport™ technology, Rapid I/O, XSBI, and SPI.