GX 010 Search Results

S82451KX

Abstract: s82452kx S82454GX s82453kx 450GX 450KX 82453KX 243109 d655 s-spec
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: April 1998 Order Number: 243109-014 The Intel 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product

U042

Abstract: S82454GX 450GX 450KX 82453KX S82451KX 243109 S82451GX 82451KX
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: October 1997 Order Number: 243109-012 The 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product to

450GX

Abstract: S82454GX 3014 LED 82450 S82452GX S82454 3554-1 pciset datasheet S82451GX U056
Contextual Info: Intel 450KX/GX PCIset Specification Update 82454KX/GX PB 82453KX/GX (MC) 82452KX/GX (DP) 82451KX/GX (MIC) Release Date: August 1998 Order Number: 243109-015 The Intel 450KX/GX PCIset may contain design defects or errors known as errata which may cause the product

B17C

Abstract: frequency divider block diagram simple block diagram for digital clock EP1AGX50DF single phase ups block diagram AGX52001-2 8b10b EP1AGX20CF
Contextual Info: 1. Arria GX Transceiver Architecture AGX52001-2.0 Introduction Arria GX is a protocol-optimized FPGA family that leverages Altera’s advanced multi-gigabit transceivers. The Arria GX transceiver blocks build on the success of the Stratix II GX family and are optimally

EP4SGX230

Abstract: EP4SGX180 EP4SGX290 EP4SGX360 EP4SGX70 receiver altLVDS EP4SGX230ES
Contextual Info: Errata Sheet for Stratix IV GX Devices ES-01022-5.5 Errata Sheet This errata sheet provides updated information about known device issues affecting Stratix IV GX devices. Production Devices for Stratix IV GX Devices Table 1 lists the specific issues and the affected Stratix IV GX production devices.

AGX52011-1

Abstract: EPC16 EPCS128 EPCS16 EPCS64
Contextual Info: 11. Configuring Arria GX Devices AGX52011-1.2 Introduction Arria GX II devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Arria GX devices each time the device powers up. Arria GX devices can

2f 1001

Abstract: 11010 OC-96
Contextual Info: 6. Specifications & Additional Information SIIGX52004-3.0 Transceiver Blocks Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Table 6–1. Stratix II GX Features Versus Stratix GX Features Part 1 of 2

10-bit-serdes

Abstract: K280A B010011 8HBC D243
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.1 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram

B17C

Abstract: 8b/10b align AGX52001-1
Contextual Info: 1. Arria GX Transceiver Architecture AGX52001-1.2 Introduction The Arria GX is a protocol-optimized FPGA family that leverages Altera ’s advanced multi-gigabit transceivers. The Arria GX transceiver blocks build on the success of the Stratix® II GX family and are optimally

Contextual Info: Errata Sheet for Arria II GX Devices ES-01025-3.7 Errata Sheet This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected. Table 1. Issues for Arria II GX Devices Part 1 of 2

EP2AGX125

Abstract: ALTMEMPHY
Contextual Info: Arria II GX Device Family ES-01025-3.1 Errata Sheet Introduction This errata sheet provides updated information about known device issues affecting Arria II GX devices. Table 1 lists the specific issues and which Arria II GX devices are affected by each

2f 1001

Abstract: 1100 11010 FD-111 transistor D313 equivalent
Contextual Info: 6. Specifications & Additional Information SIIGX52004-3.1 Transceiver Blocks Table 6–1 shows the transceiver blocks for Stratix II GX and Stratix GX devices and compares their features. Table 6–1. Stratix II GX Features Versus Stratix GX Features Part 1 of 2

EP2SGX60EF

Abstract: CEI 23-16 circuit diagram of PPM transmitter and receiver CPRI multi rate HD-SDI over sdh PRBS10 3G-SDI serializer SIIGX52002-4 k307
Contextual Info: 2. Stratix II GX Transceiver Architecture Overview SIIGX52002-4.2 Introduction This chapter provides detailed information about the architecture of Stratix II GX devices. Figure 2–1 shows the Stratix II GX block diagram. Figure 2–1. Stratix II GX Transceiver Block Diagram

AGX52011-1

Abstract: EPC16 EPCS128 EPCS16 EPCS64
Contextual Info: 11. Configuring Arria GX Devices AGX52011-1.3 Introduction Arria GX II devices use SRAM cells to store configuration data. Because SRAM memory is volatile, configuration data must be downloaded to Arria GX devices each time the device powers up. Arria GX devices can

Contextual Info: SK 3 THYRISTOR BRIDGE,SCR,BRIDGE Axial Lead Diode 3$GH 3$$H 3 0222 0Z22 0E22 3 0222 0Z22 0E22 GX RY02 GX RY0Z GX RY0E 0122 0122 GX RY01 SK 3 Features # $%&%' % & *+,-%( ./ +) 0122 3 # 4,/%5 6)' ,.+)7,+89 8:(%'+8): # ;&,8*,<*% =8+> 6)'7%5 *%,5( ): # '%?.%(+

HD-SDI over sdh

Abstract: GR-253-CORE PRBS31 SMPTE292M SSTL-15 SSTL-18 PRBS-15
Contextual Info: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Device Datasheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook

Contextual Info: Section I. Arria II GX Device Data Sheet and Addendum This section provides information about the Arria II GX device data sheet and addendum. This section includes the following chapters: • Chapter 1, Arria II GX Devices Data Sheet ■ Chapter 2, Addendum to the Arria II GX Device Handbook

free verilog code of prbs pattern generator

Abstract: CPRI multi rate digital alarm clock vhdl code 10 band graphic equalizer CEI 23-16 diode handbook HD-SDI over sdh SDH 209 vhdl code for 16 prbs generator vhdl code for phase frequency detector for FPGA
Contextual Info: Section I. Stratix II GX Transceiver User Guide This section provides information on the configuration modes for Stratix II GX devices. It also includes information on testing, Stratix II GX port and parameter information, and pin constraint information.

B17C

Abstract: Chapter 3 Synchronization diode handbook SDI SERIALIZER Semiconductor Reference and Application Handbook AGX52001-2 Voltage-controlled oscillator hd-SDI deserializer LVDS EP1AGX50DF
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:

circuit diagram of inverting adder

Abstract: KR 108 6621 3.3V
Contextual Info: Stratix GX FPGA Family Data Sheet December 2004, ver. 2.2 Introduction The Stratix GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

b17c

Abstract: AGX52001-1 AGX52002-1 PMD 1000
Contextual Info: Section I. Arria GX Transceiver User Guide This section provides information on the configuration modes for Arria GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information. This section includes the following chapters:

SSTL-18

Contextual Info: Stratix GX November 2002, ver. 1.0 Introduction FPGA Family Data Sheet Preliminary Information The StratixTM GX family of devices is Altera’s second FPGA family to combine high-speed serial transceivers with a scalable, high-performance logic array. Stratix GX devices include 4 to 20 high-speed transceiver

Serial RapidIO Infiniband

Abstract: k307 K284
Contextual Info: 2. Stratix GX Transceivers SGX51002-1.1 Transceiver Blocks Stratix GX devices incorporate dedicated embedded circuitry on the right side of the device, which contains up to 20 high-speed 3.1875-Gbps serial transceiver channels. Each Stratix GX transceiver block contains

RTL code for ethernet

Abstract: transistor h5c verilog code of prbs pattern generator barrel shifter block diagram free verilog code of prbs pattern generator verilog code for 10 gb ethernet SGX52001-1 SGX52005-1
Contextual Info: Section I. Stratix GX Transceiver User Guide This section provides information on the configuration modes for Stratix GX devices. It also includes information on testing, Stratix GX port and parameter information, and pin constraint information. This section includes the following chapters: