GS8342T Search Results

Contextual Info: GS8342TT07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: Preliminary GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342T06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package

Contextual Info: GS8342TT07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaCIO DDR-II Burst of 2 SRAM 300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Military Temperature Range • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: Preliminary GS8342TT07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaDDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: Preliminary GS8342T06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

GS8342TT38

Contextual Info: GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: Preliminary GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package

Contextual Info: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaDDR-II Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8342T08/09/18/36AE-333/300/250/200/167 36Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS8342T06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8342T07/10/19/37BD-450/400/350/333/300 36Mb SigmaDDR-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: Preliminary GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package

Contextual Info: GS8342T08/09/18/36AE-300M 165-Bump BGA Military Temp 36Mb SigmaDDR-II Burst of 2 SRAM Features • Military Temperature Range • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8342T08/09/18/36AE-250/200/167 36Mb SigmaDDR-II Burst of 2 SRAM • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write x36, x18, and x9 and Nybble Write (x8) function

GS8342T36BGD-250

Contextual Info: Preliminary GS8342T08/09/18/36BD-400/350/333/300/250 36Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface