FPQ 208 0.5 10 Search Results

FPQ 208 0.5 10 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
FPQ 208 0.5 10 Abstract: FPQ Package FPQ-256 FPQ 240 FPQ-240-0 FPQ-240-0.5 FPQ-48-0 FPQ-52-0.65-01A 52 FPQ-64 FPQ-44-0 Text: QFP QUAD FLAT PACKAGE ORDERING PROCEDURE FPQ □□□ □. □□ □□ Design NO. Pitch Pin Count Socket Series SPECIFICATIONS Contact resistance: Initial 30mΩ At 10 mA Maximum voltage: AC700V RMS (for 1 minute) Below 0.5mm Pitch	Original	PDF	AC700V AC500V FPQ-44-0 FPQ-44-0. FPQ 208 0.5 10 FPQ Package FPQ-256 FPQ 240 FPQ-240-0 FPQ-240-0.5 FPQ-48-0 FPQ-52-0.65-01A 52 FPQ-64
ERC32 Abstract: CB123 CY7C601 TSC691E TSC692E TSC693E FPU-TSC692E erc32 trap 0x61 TMS 3529 A1191 Text: TSC691E Integer Unit User’s Manual for Embedded Real time 32–bit Computer ERC32 for SPACE Applications TSC691E Table of contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1	Original	PDF	TSC691E ERC32) TSC691E ERC32 CB123 CY7C601 TSC692E TSC693E FPU-TSC692E erc32 trap 0x61 TMS 3529 A1191
erc32 trap 0x61 Abstract: Cy7C601 ERC32 CB123 TSC691E TSC692E TSC693E tbr 3516 SPARC V7.0 Text: TSC691E Integer Unit User’s Manual for Embedded Real time 32–bit Computer ERC32 for SPACE Applications TSC691E Table of contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1	Original	PDF	TSC691E ERC32) TSC691E ERC32 erc32 trap 0x61 Cy7C601 CB123 TSC692E TSC693E tbr 3516 SPARC V7.0
ERC32 Abstract: sparc v7 CB123 TSC691E TSC692E TSC693E erc32 trap 361-s SPARC V7.0 Text: TSC691E Integer Unit User’s Manual for Embedded Real time 32–bit Computer ERC32 for SPACE Applications TSC691E Table of Contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1	Original	PDF	TSC691E ERC32) TSC691E ERC32 sparc v7 CB123 TSC692E TSC693E erc32 trap 361-s SPARC V7.0
ird8 Abstract: LRD12 54SX32 ic tny 176 TNY 227 TNY 251 Text: ^ c te l P re lim in a ry v l.1 54SX Family FPGAs RadTolerant and HiRel F e a tu re s R a d T o le r a n t 5 4 S X F a m ily • • • • • Tested Total Ionizing Dose TID Survivability Level Devices Available from Tested Lots Radiation Performance to 100K Rads	OCR Scan	PDF
rd8 f01 ad Abstract: MOCK Text: Æ k ù iil Accelerator Series FPGAs ACT 3 PCI-Compliant Family • HI m*S M F e a tu re s • Up to 10,000 Gate Array Equivalent Gates. • Highly Predictable, Synthesis-Friendly Architecture Supports High-Level Design Methodologies. . Up to 250 MHz On-Chip Performance.	OCR Scan	PDF	20-Pin 16-Bit) 10Kresistorlo rd8 f01 ad MOCK
Untitled Abstract: No abstract text available Text: v3.0 SX-A Family FPGAs Leading-Edge P erfo rm an c e • 250 MHz System Performance • 3.8ns Clock-to-Out Pad-to-Pad • 350 MHz Internal Performance S p ec ific atio n s • • • • 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins	OCR Scan	PDF	22p/0
A1020 Y Abstract: smd transistor E5 GHL 88 Text: Military Field Programmable Gate Arrays Features A C T 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family • System Performance to i( MHz over Military Temperature	OCR Scan	PDF	20-pin A1020 Y smd transistor E5 GHL 88
B12C3 Abstract: LA1240 Text: Integrator Series FPGAs - 1200XL and 3200DX Familes F e a tu re s Cadence, Escalade, Exemplar, 1ST, Mentor Graphics, Synopsys and Viewlogic H ig h C a p a c ity • JTAG 1149.1 Boundary Scan Testing • 2,500 to 40,000 logic gates • Up to 4 Kbits configurable dual-port SRAM	OCR Scan	PDF	1200XL 3200DX 35-bit 3200D B12C3 LA1240
SPARC V7.0 Abstract: TSC692 Text: Temic S e m i c o n d u c t o r s TSC691E Integer Unit User’s Manual for Embedded Real time 32-bit Computer ERC32 for SPACE Applications Temic S em i co n du ct o r s TSC691E Table of contents 1. I n t r o d u c t i o n .1	OCR Scan	PDF	TSC691E 32-bit ERC32) Fault44 SPARC V7.0 TSC692