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micrologic

Abstract: gating a signal using NAND gates fairchild micrologic IC953 slave and master inverter circuit diagrams Inverter Gates CA2TC CTVL952 pin configuration of logic gates logic gates circuit diagram
Contextual Info: • M ARCH 1965 CT mL952 THROUGH CTgL957 9 TRANSISTOR COMPLEMENTARY TRANSISTOR MICROLOGIC INTEGRATED CIRCUITS MICROLOGIC® G E N E R A L D E S C R IP T IO N - The Fairchild CT/aL Fam ily was designed for very high-speed, low -cost com m ercial system s applications.

VSC715

Contextual Info: ICS9536-01 Integrated Circuit Systems, Inc. Advanced Information 1.0625GHz CMOS Fibre Channel Transceiver General Description Features CMOS technology provides lowest cost and power Pin compatible with HDMP-1536 Bipolar and VSC7125 (GaAs) fibre channel transceivers

LTC2934-2

Abstract: F02MR LTC2934-1 CR2032 3.3V battery
Contextual Info: LTC2934 Ultra-Low Power Adjustable Supervisor with Power-Fail Output DESCRIPTION FEATURES n n n n n n n n n 500nA Quiescent Current ±1.5% Max Accuracy over Temperature Operates Down to 1.6V Supply Adjustable Reset Threshold Adjustable Power-Fail Threshold

ramps 1.4

Abstract: variable dutycycle square wave generator circuit square pulse generator ic variable frequency generator GSA-1000 PB104 sine generator ic UBS-100 SWEEP GENERATOR IC QT-59S
Contextual Info: G l o b a l Specialties Breadboarding Systems and Test Instruments 2001A Low Cost Function Generator c c c c c c c 2020A Oscilloscope 4001 Digital Pulse Generator 5 MHz Ultra-Variable Generator Exceptionally Low Sine Wave Distortion Sine, Square, Triangle Plus TTL Outputs

30 pin flex cable lcd

Abstract: AN-1126 LM2507 LM2507GR LM2507SQ
Contextual Info: LM2507 Low Power Mobile Pixel Link MPL Level 0, 16-bit CPU Display interface Serializer and Deserializer General Description Features The LM2507 device adapts i80 CPU style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. When using smart CPU type interfaces, two chip selects support a

Contextual Info: October 25, 2011 LM2507 Low Power Mobile Pixel Link MPL Level 0, 16-bit CPU Display Interface Serializer and Deserializer General Description Features The LM2507 device adapts i80 CPU style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. When

SAB 82258

Abstract: dv3c Dwo1 pin diagram priority encoder 74146 82258 DV12C FSV 052 interfacing 8289 with 8086 8283A DX14C
Contextual Info: SAB 82220 Bus Interface Controller BIC • H ighly integrated m icroprocessor system support com ponent • Six modes o f operation fo r flexible adaption to different applications • Integrates into one package m icroprocessor interface logic, like bus drivers, bus control

LT1220

Contextual Info: «M BTD ÄL B i L E Ä S E Final Electrical Specifications l T E C L T C 1 2 7 4 / L T C 1 2 7 7 m i H N O L O G Y A D C 1 2 - B i t , l O s 1 [ ¿ A w i t h m W S , l O h u O t d k s p s o w n J u n e 1995 KATURCS DCSCRIPTIOn • Low Power Dissipation: 10mW Typical

Contextual Info: LM2507 LM2507 Low Power Mobile Pixel Link MPL Level 0, 16-bit CPU Display Interface Serializer and Deserializer Literature Number: SNVS439A October 25, 2011 LM2507 Low Power Mobile Pixel Link (MPL) Level 0, 16-bit CPU Display Interface Serializer and Deserializer

pcie sas

Abstract: 10G-KR CHA200 SAS3 STA280
Contextual Info: DS125BR800 Low Power 12.5 Gbps 8-Channel Repeater with Input Equalization and Output De-Emphasis General Description Features The DS125BR800 is an extremely low power, high performance multi-protocol repeater/redriver designed to support 8 channels of SAS-3/2/1, PCIe Gen-3/2/1, 10G-KR and other

Contextual Info: DS125BR800 Low Power 12.5 Gbps 8-Channel Repeater with Input Equalization and Output De-Emphasis General Description Features The DS125BR800 is an extremely low power, high performance multi-protocol repeater/redriver designed to support 8 channels of SAS-3/2/1, PCIe Gen-3/2/1, 10G-KR and other

Contextual Info: Æ X - VSB 1400 T• VSB Master Module Interface Device May 1989_ Distinctive Features_ Applications_ • Bus interface circuitry for multi-master VSB systems • VSB master chip contains - Single level arbiter

Step-up 12V to 36V 300mA

Abstract: current limit switch 12V Step-up 12V to 36V CS1615 CS1615-1
Contextual Info: CS1615 Micropower Step-up DC/DC Converters for White LEDS Features z Low Quiescent Current: z z z z z 20 A in Active Mode <1μA in Shutdown Mode Operates with VIN as Low as 1V Low VCESAT Switch: 250mV at 300mA Uses Small Surface Mount Components High Output Voltage: Up to 34V

00I-4

Abstract: W24257AS-35
Contextual Info: W24257A inbond W= = ^ ^ = = = = ^ éès = ^ =êè^ eM Electronics Corp. 32K X 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W24257A is a high speed, low power C M O S static RAM organized as 32768 x 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high

remote control tx-2b

Abstract: tx 2b
Contextual Info: December, 1995 SK70704/SK70706 784 kbps HDSL Data Pump Chip Set General Description Features The HDSL Data Pump is a chip set consisting o f the fol­ lowing two devices: . SK70704 Analog Core Chip ACC . SK70706 HDSL Digital Transceiver (HDX) The HDSL Data Pump is a 2-wire transceiver which pro­

Contextual Info: VSB 1400 Æ X - VSB Master Module Interface Device Tu May 1989_ Distinctive Features_ Applications_ • Bus interface circuitry for multi-master VSB systems • VSB master chip contains - Single level arbiter

SK70704PE

Abstract: LTU 455 E 2
Contextual Info: — — -— SK70704/SK70707 U M ì — APRIL, 1996 1168 kbps HDSL Data Pump Chip Set ieneral Description :eatures The HDSL Data Pump is a chip set consisting o f the fol­ lowing two devices: • SK70704 Analog Core Chip ACC • SK70707 HDSL Digital Transceiver (HDX)

Contextual Info: iw SGS-THOMSON [ » im iiû f lÎM O Û S 7 4 L C X 1 6 3 7 4 A LOW VOLTAGE 16-BIT D-TYPE FLIP FLOP 3-STATE _ WITH 5V TOLERANT INPUTS AND OUTPUTS PRELIMINARY DATA 5V TOLERANT INPUTS AND OUTPUTS HIGH SPEED: fMAX = 170 MHz MIN. at Vcc = 3V POWER-DOWN PROTECTION ON INPUTS

16c450 rs485

Abstract: "2,4GHz wireless rs485" diagram RN-121-TEMP analog sensor RN-125 temperature wireless sensor pcb
Contextual Info: RN-121, RN-122, RN-123 & RN-125 www.rovingnetworks.com rn-121-ds 9/22/2009 “WiFly GX” 802.11G Super Module Features • 802.11b/g PHY/MAC at up to 54Mbps • Qualified 2.4GHz IEEE 802.11b/g transceiver • Wi-Fi Alliance certified for WPA2-PSK • Ultra-low power - 4uA sleep, 40mA Rx,

DS100BR410

Contextual Info: DS100BR410 www.ti.com SNLS326A – OCTOBER 2010 – REVISED MARCH 2012 DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and DeEmphasis Driver Check for Samples: DS100BR410 FEATURES • 1 • • 2 • • • • • Quad channel repeater for up to 10.3125 Gbps

Contextual Info: DS100BR410 www.ti.com SNLS326B – OCTOBER 2010 – REVISED APRIL 2013 DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and DeEmphasis Driver Check for Samples: DS100BR410 FEATURES APPLICATIONS • • • • • 1 2 • • • •

LTCL

Abstract: LT1220
Contextual Info: iy I Final Electrical Specifications L l l i C A LTC1274/LTC1277 12-Bit lOmW, lOOksps A D C s w ith 1|iA S h u td o w n I c TECHNOLOGY J u n e 1995 FCftTURCS l €SCRIPTIOn • Low Power Dissipation: 10mW Typical ■ Sample Rate: 100ksps ■ Samples Inputs Well Beyond Nyquist, 71 dB S/ N + D)

Contextual Info: DS100BR410 www.ti.com SNLS326B – OCTOBER 2010 – REVISED APRIL 2013 DS100BR410 Low Power Quad Channel Repeater with 10.3125 Gbps Equalizer and DeEmphasis Driver Check for Samples: DS100BR410 FEATURES APPLICATIONS • • • • • 1 2 • • • •

gi 9344 diode

Abstract: 752-R
Contextual Info: AUGUST 1997 Revision 3.0 SK70704/SK70707 or SK70708 1168 kbps HDSL Data Pump Chip Set General Description Features The HDSL Data Pump is a chip set consisting of the fol­ lowing two devices: • SK70704 Analog Core Chip ACC • SK70707 (68-pin PLCC) or SK70708 (44-pin PLCC)