FLIP-FLOPS D Search Results

1D10

Abstract: HD74ALVCH16821 Hitachi DSA003731
Contextual Info: HD74ALVCH16821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs ADE-205-171B Z 3rd. Edition December 1999 Description The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

Contextual Info: HD74ALVCH16821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-171A Z 2nd. Edition September 1997 Description The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

Hitachi DSA0095

Abstract: 1D10 HD74ALVCH162821
Contextual Info: HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs ADE-205-186A Z 2nd. Edition September 1997 Description The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

Hitachi DSA00164

Contextual Info: HD74ALVCH16821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs ADE-205-171A Z 2nd. Edition September 1997 Description The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

Contextual Info: HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-186A Z 2nd. Edition September 1997 Description The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

FAIRCHILD MM74HC

Abstract: 74HC MM54HC MM54HC174 MM74HC MM74HC174
Contextual Info: MM74HC174 Hex D Flip-Flops with Clear General Description These edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flip-flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave flip-flops with a common clock and

Hitachi DSA002744

Contextual Info: HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs ADE-205-186A Z 2nd. Edition September 1997 Description The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

Contextual Info: HD74ALVCH162821 3,3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-186A Z 2nd. Edition September 1997 Description The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

Contextual Info: HD74ALVCH162821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-186 Z Preliminary 1st. Edition December 1996 Description The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device

Contextual Info: HD74ALVCH16821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs HITACHI ADE-205-171 Z Preliminary, 1st. Edition January 1997 Description The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides

74LS273

Contextual Info: Sjgnetìcs 74LS273, S273 Flip-Flops Octal D Flip-Flops Product Specification Logic Products FEATURES TYPE • Ideal buffer for MOS microprocessor or memory • Eight edge-triggered D flip-flops • High speed Schottky version available • Buffered common clock

Contextual Info: MM54HC174/MM74HC174 Hex D Flip-Flops with Clear General Description Features These edge triggered flip-flops utilize advanced silicon-gate CMOS technology to Implement D-type flip-flops. They pos­ sess high noise Immunity, low power, and speeds compara­

54175

Abstract: D313F
Contextual Info: Signetics 54175, 54LS175 Flip-Flops Quad D Flip-Flops Military Logic Products FEATURES • Four edge-triggered D flip-flops • Three speed-power ranges available • Buffered common clock • Buffered, asynchronous Master Reset DESCRIPTION The 54175 and 54LS175 are quad,

Contextual Info: HD74ALVCH162820 3.3-V 10-bit Flip Flops with Dual Outputs and 3-state Outputs HITACHI ADE-205-185 Z Preliminary 1st. Edition December 1996 Description The HD74ALVCH162820 flip flops are edge triggered D-type flip flops. On the positive transition of the

54175

Abstract: 54174DMQB 54174FMQB DM54174J DM54174W DM74174 DM74174N DM74175 J16A N16E
Contextual Info: EM ICONDUCTQ R t DM74174, DM74175 Hex/Quad D Flip-Flops with Clear 175 contains fo u r flip-flops w ith double-rail outputs General Description These positive-edge triggered flip-flops utilize T T L circuitry to im plem ent D -type flip-flop logic. All have a direct clear input,

Contextual Info: GD54/74LS73A DUAL NEGATIVE EDGE-TRIGGERED MASTER-SALVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS Description Pin Configuration This device contains two independent negativeedge-triggered J-K flip-flops with complementary out­ puts. The J and K data is processed by the flip-flops

74175n

Abstract: 74174N 54175 54174J
Contextual Info: EM ICONDUCTQ R t DM74174, DM74175 Hex/Quad D Flip-Flops with Clear • 175 contains fo u r flip-flops w ith double-rail outputs General Description These positive-edge triggered flip-flops utilize T T L circuitry to im plem ent D -type flip-flop logic. All have a direct clear input,

5473DMQB

Abstract: 5473 DM5473J DM7473 DM7473N 5473FMQB DM5473W J14A N14A W14B
Contextual Info: 5473 DM5473 DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops after a complete clock

DM74S74

Abstract: DM74S74M DM74S74N M14A MS-001 N14A
Contextual Info: Revised April 2000 DM74S74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the

DM74LS74A

Abstract: DM74LS74AM DM74LS74AN DM74LS85ASJ M14A M14D MS-001 N14A DSA0010771
Contextual Info: Revised March 2000 DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the

DM7474

Abstract: DM7474M DM7474N M14A MS-001 N14A
Contextual Info: Revised February 2000 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on

DM7474

Abstract: DM7474M DM7474N M14A MS-001 N14A
Contextual Info: Revised July 2001 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on

"J-K Flip flops"

Abstract: "J-K Flip flops" datasheet DM7473 DM7473N MS-001 N14A
Contextual Info: Revised February 2000 DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock

"J-K Flip flops" datasheet

Abstract: DM7473N DM7473 MS-001 N14A
Contextual Info: Revised July 2001 DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock