FLIP-FLOP SR Search Results

sr flip flop

Abstract: S-R flip flop clock high frequency flip flop
Contextual Info: PSoC Creator Component Datasheet SR Flip Flop 1.0 Features • Clocked for safe use in synchronous circuits. • Configurable width for array of SR Flip Flops. General Description The SR Flip Flop stores a digital value that can be set or reset. When to Use an SR Flip Flop

4 input d flip flop

Abstract: D Flip Flops D flip flop "D Flip Flops"
Contextual Info: PSoC Creator Component Datasheet D Flip Flop 1.30 Features • Asynchronous reset or preset • Synchronous reset, preset, or both  Configurable width for array of D Flip Flops General Description The D Flip Flop stores a digital value. When to Use a D Flip Flop

74ALS

Abstract: 74ALS74A ALS74A N74ALS74AD N74ALS74AN
Contextual Info: 74ALS74A FLIP-FLOP 74ALS74A Dual D-Type Flip-Flops with Set and Reset Product Specification DESCRIPTION The 'ALS74A is a dual edge-triggered Dly p e flip-flop featuring individual data, Set and Reset inputs, w ithjrue and comqlementary outputs. Set SD and Reset (R0)

D Flip Flops

Contextual Info: PSoC Creator Component Datasheet D Flip Flop 1.20 Features • Asynchronous reset or preset • Synchronous reset or preset  Optional array of D Flip Flops  Can be configured for different width General Description The D Flip Flop stores a digital value.

74f50729

Contextual Info: Signetics FAST 74F50729 FLIP-FLOP FAST Products FEATURES • Metastable Immune Characteris­ tics • Propagation delay skew and output to output skew less than 1.5ns • See 74F5074 lor Synchronizing Dual D-Type Flip-Flop > See 74F50109 for Synchronizing

Contextual Info: S lgnetics FAST 7 4 F 1 12 Docum ent No. 853-0338 EON No. 98775 Date of issue February 9 ,1 9 9 0 Status Product Specification Flip-Flop Dual J-K Negative Edge-triggered Flip-Flop FAST Products "1 I -

Contextual Info: INTEGRATED CIRCUITS 74LVT16374A 3.3V LVT 16-bit edge-triggered D-type flip-flop 3-State Product data sheet Supersedes data of 2002 Nov 01 Philips Semiconductors 2004 Sep 16 Philips Semiconductors Product data sheet 3.3V 16-bit edge-triggered D-type flip-flop

74lvt16374a

Abstract: TSSOP48 VFBGA56 2D21 74LVT16374AEV SSOP48
Contextual Info: INTEGRATED CIRCUITS 74LVT16374A 3.3V LVT 16-bit edge-triggered D-type flip-flop 3-State Product data Supersedes data of 1999 Oct 18 Philips Semiconductors 2002 Nov 01 Philips Semiconductors Product data 3.3V 16-bit edge-triggered D-type flip-flop (3-State)

74lvt16374a

Abstract: 2D21 74LVT16374ADGG 74LVT16374ADL 74LVT16374AEV SSOP48 TSSOP48 VFBGA56
Contextual Info: INTEGRATED CIRCUITS 74LVT16374A 3.3V LVT 16-bit edge-triggered D-type flip-flop 3-State Product data sheet Supersedes data of 2002 Nov 01 Philips Semiconductors 2004 Sep 16 Philips Semiconductors Product data sheet 3.3V 16-bit edge-triggered D-type flip-flop

Contextual Info: CY7C331 CYPRESS — . = SEMICONDUCTOR Asynchronous Registered EPLD T\velve I/O macrocells each having: — One state flip-flop with an XOR sura-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set,

Contextual Info: TOSHIBA 14E O I *10T?2Ma 0010335 b | LOGIC/MEMORY TC74HC377P/F TC74HC377P/F OCTAL D-TYPE FLIP-FLOP The TC74HC377 Is high speed CMOS D-TYPE FLIP-FLOP fabricated with silicon C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining

TRANSISTOR tr4

Abstract: SP1670 TR10 TR11 TR21 TR22 TR23 TR25 TR26 TR30
Contextual Info: SP1670 SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Mastfer-slave construction renders the SP1670 relatively insensitive to the shape of the clock waveform, since only the voltage levels at

Contextual Info: TOSHIBA C2MOS Logic TC74LCX574F/FW/FS Low Voltage Octal D-Type Flip Flop with 5V Tolerant Inputs and Outputs The TC74LCX574 is a high performance CMOS OCTAL DTYPE FLIP FLOP. Designed for use in 3.3 Volt systems, it achieves high speed operation while maintaining the CMOS

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

7c331-35

Contextual Info: s :^é= , CY7C331 •jS QYPRESS -■ W SEMICONDUCTOR Asynchronous Registered EPLD Features • TVelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

RQW 130

Abstract: tlOH-tm33X ELLS 110 CY7C331
Contextual Info: i*bE ]> CYPRESS SEMICONDUCTOR B 256*^1.2 DDQ7Q5Q 7 Q C Y P c t 7C33i CYPRESS SEMICONDUCTOR Asynchronous Registered EPLD Features • Tnelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — O ne feedback flip-flop with input

Contextual Info: f Z T SGS-THOMSON Ä T# HCC/HCF4013B IM E[HÎ(3 ilLi(OTM D(3S DUAL ’D' - TYPE FLIP-FLOP . SET-RESET CAPABILITY . STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ’’HIGH” OR "LOW” • MEDIUM-SPEED OPERATION - 16MHz (typ.)

T12D diode

Contextual Info: Order thl» data sheet by MC20LX374/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC20LX374 20-Bit D-Type Flip-Flop 3-State9 Non-Inverting WT HiHli » Features • A Member of Motorola’s ALExIS Bus Interface Solutions Family 20-BIT D-TYPE FLIP-FLOP (3-STATE, NON-INVERTING)

61S11

Contextual Info: fax id: 6016 CY7C331 CYPRESS Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock in­

Contextual Info: ^a rc h "f., jQ Q Q Revised April 1999 74LCX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs General Description Features T h e LCX74 is a dual D -type flip-flop with Asynchronous C lear and Set inputs and com plem entary Q, Q outputs.

EI24

Abstract: GI05 st C331 n 332 ab EI-24
Contextual Info: _ ~ 2 r CY7C331 •^CYPRESS Features • 13 inputs, 12 feedback I/O pins, plus 6 • Twelve I/O macrocells each having: — One stale flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set,

Contextual Info: M M O T O R O LA Military 10535 Dual J-K Master Slave Flip-Flop ELECTRICALLY TESTED PER: MIL-M-38510/06104 Th e 10535 is a dual m aster-slave dc coupled J- K flip-flop. Asynchronous Set (S ) and R eset (R ) are provided. Th e set and reset inputs override the clock.

Contextual Info: M M C 74A C 825 M C 74A C T 825 M O T O R O L A Product Preview 8-Bit D -Type Flip-Flop 8-BIT D-TYPE FLIP-FLOP The MC74AC825/74ACT825 is an 8-bit buffered register. It has Clock Enable and Clear features w hich are ideal for parity bus interfacing in high performance micro­

Contextual Info: ATV5000/L Features • • • • • • Advanced Programmable Logic Device - High Gate Utilization Flexible Interconnect Architecture - Universal Routing Flexible Logic Cells -128 Flip-Flops and 52 Latches Multiple Flip-Flop Types - Synchronous or Asynchronous Registers