FLIP-FLOP 1 GHZ Search Results

MC100EL35

Contextual Info: bPE D MOTOROLA m SEMICONDUCTOR b3b?25E OG^SObö 73b IM0T4 MOTOROLA SC LOGIC 1 TECHNICAL DATA JK Flip-Flop MC10EL35 MC100EL35 The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is

CXB1109Q

Abstract: MR510 CXB1109
Contextual Info: CXB1109Q SONY. Quad D Flip-Flop with M aste r Reset and Differential I/O Description Pin Assignment The C X B 1 1 0 9 Q is an ultra high speed monolithic E C L IC, which contains four D Flip-Flop’s. Positive edge of M aster Clock Ca and Cb triggers the Flip-Flop’s, and M aster Reset M R resets them.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA D Flip-Flop With Set and Reset MC10EL31 MC100EL31 T h e M C 1 0 E U 1 0 0 E L 3 1 is a D flip-flop with set and reset. T h e device is functionally equ ivalent to the E131 capabilities. W ith propagation device with higher perform ance

Contextual Info: Freescale Semiconductor Technical Data Document Number: MC100ES6030 Rev 1, 09/2005 3.3 V ECL Triple D Flip-Flop with Set and Reset MC100ES6030 The MC100ES6030 is a triple master-slave D flip-flop with differential outputs. When the clock input is low, data enters the master latch and transfers to the

Contextual Info: MOTORO'-A SEMICONDL CTOR TECHNICAL DATA Differential D ata and Clock D Flip-Flop M C10EL52 M C100EL52 The IMC10EL/1 0E:L52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the E452 device with higher performance capabilities. With propagation delays and output

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY S E M IC O N D U C T O R DESCRIPTION FEATURES • 525ps propagation delay The S Y 10 /1 00EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip -flop when the clock is LO W and is tran sfe rre d to the slave and,

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA A d va n ce Inform ation M C 1 0 0 LVEL2 9 M C 1 0 0 EL2 9 Dual Differential Data and Clock D Flip-Flop With Set and Reset The MC100LVEL29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100EL29

DNA 1005

Abstract: selic NLB6223 ECL100K flip flop
Contextual Info: NLB6223 Quad Flip Flop with 2 : 1 Selector NEL SELIC Description The NLB6223 is an ultra high-speed monolithic quad D Flip-Flops with 2:1 Selector. Features • Typical clock rate up to 2.0 GHz. • Internal pull down resistors on input pins DnA, DnB,SELP, CKP to maintain logic

MC100E167

Abstract: 100E167 MC100E167FN MC100E167FNR2 MC10E167 MC10E167FN MC10E167FNR2
Contextual Info: MC10E167, MC100E167 5VĄECL 6ĆBit 2:1 MuxĆRegister The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop

MC100E167

Abstract: MC100E167FN MC100E167FNR2 MC10E167 MC10E167FN MC10E167FNR2
Contextual Info: MC10E167, MC100E167 5VĄECL 6ĆBit 2:1 MuxĆRegister The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop

lee 323-m

Abstract: E131 SY100EL31 SY10EL31 SY10EL31ZC
Contextual Info: *SYNERGY D FLIP-FLOP WITH SET AND RESET SY10EL31 SY100EL31 S E M IC O N D U C T O R DESCRIPTION FEATURES The S Y 1 0 /1 OOEL31 are D flip -flop s w ith set and reset. T he device s are fu n c tio n a lly e q u iva le n t to th e E131 d e vice s, w ith h ig h e r p e rfo rm a n ce c a p a b ilitie s .

mc100ep31dtg

Abstract: DFN8 HEP31 MC10EP31 MC100EP31DG MC100EP31
Contextual Info: MC10EP31, MC100EP31 3.3V / 5V ECL D Flip-Flop with Set and Reset Description MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 Features The 100 Series contains temperature compensation. • 340 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical

UPG706

Contextual Info: NEC HIGH SPEED MASTER/SLAVE D FLIP-FLOP OUTLINE DIMENSIONS FEATURES UPG706B-1 UPG706B-2 Units in mm • ECL COMPATIBLE • ULTRA HIGH SPEED AND HIGH INPUT SENSITIVITY fMAx = 4 GHz MIN at ECL Input Level (UPG706B-1, -2) OUTLINE H16 • HERMETICALLY SEALED CERAMIC PACKAGE

d 2331

Abstract: half adder ic number of half adder ic with full specification vts 7070
Contextual Info: VITESSE SEMICONDUCTOR MflE D VITESSE FEATURES • Superior performance: high speed/low power • Array performance: - D flip-flop toggle rates: >1 GHz - Typical gate delay: 177 ps @ 1.1 mW 2-Input NOR, F.O. = 3 ,1 .5 mm wire - TTL/CM O S inputs/outputs to support up to

Contextual Info: HMC-C061 v02.0711 50 Gbps, DOUBLE-EDGE TRIGGERED D-TYPE FLIP-FLOP MODULE Features Supports data rates 50 Gbps Half Rate Clock Input 1 MHz - 25 GHz Inputs Terminated Internally in 50 ohms Supports Single-Ended or Differential Operation Very Low Power Consumption: 690 mW

Contextual Info: HMC-C061 v01.0109 50 Gbps, DOUBLE-EDGE TRIGGERED D-TYPE FLIP-FLOP MODULE Features Supports data rates 50 Gbps Half Rate Clock Input 1 MHz - 25 GHz Inputs Terminated Internally in 50 ohms Supports Single-Ended or Differential Operation Very Low Power Consumption: 690 mW

Contextual Info: HMC-C061 v02.0711 50 Gbps, DOUBLE-EDGE TRIGGERED D-TYPE FLIP-FLOP MODULE Features Supports data rates 50 Gbps Half Rate Clock Input 1 MHz - 25 GHz Inputs Terminated Internally in 50 ohms Supports Single-Ended or Differential Operation Very Low Power Consumption: 690 mW

Contextual Info: When Every Pico Second Counts 1:9 Differential Clock Driver SK10/100E131 4-Bit D Flip-Flop SK10/100E142 9-Bit Shift Register SK10/100LVE111 Low-Voltage 1:9 Differential ECL/PECL Clock Driver with enable input SK10/100EP111 Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver

LT1038

Contextual Info: High Performance 2400 Gate TTL Compatible GaAs Gate Array FEATURES • Superiorperformance: high speed/low power • Array performance: - D flip-flop toggle rates: >1 GHz - Typical gate delay: 177 ps @ 1.1 mW 2-Input NOR, F.O. = 3,1 .5 mm wire - TTL/CMOS inputs/outputs to support up to

E452

Abstract: KEL52 MC100EL52 MC10EL52
Contextual Info: MC10EL52, MC100EL52 5V ECL Differential Data and Clock D Flip-Flop Description http://onsemi.com MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 1 1 1 > 100 V Machine Model • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V • • • • • • • with VEE = 0 V

T-type flip flop

Abstract: CI0084 NTT Electronics GaAs
Contextual Info: GD-01-1-60-42-121A CI0084 16 May 2002 PRELIMINARY 43 GHz T-FF Features Maximum operating frequency: 43 GHz Output amplitude: 0.9 Vpp Single-ended clock input General Description The CI0084 is a dynamic T-type Flip Flop T-FF operating at rates from 20 GHz to 43

E151

Abstract: HEL51 KEL51 MC100EL51 MC10EL51
Contextual Info: MC10EL51, MC100EL51 5V ECL Differential Clock D Flip-Flop Description Features http://onsemi.com MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 8 HEL51 ALYW G 1 1 1 8 HL51 ALYWG G 4X M G G > 100 V Machine Model • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V

Contextual Info: CXB1509Q-Y SONY. Quad D Flip-Flop w ith M a ster Reset and D ifferen tial I/O Description Pin A ssignm ent Th e C X B 1 5 0 9 Q - Y is a n ultra h ig h spe e d m onolithic E C L IC, w hich c o n ta in s fo u r D Flip-Flop’s. NC 01 01 01 01 02 02 NC P o s itiv e e dge o f M a st e r C lo c k C * a n d C b trig g e rs

HEL52

Abstract: KEL52 E452 MC100EL52 MC10EL52
Contextual Info: MC10EL52, MC100EL52 5V ECL Differential Data and Clock D Flip-Flop Description Features http://onsemi.com MARKING DIAGRAMS* 8 1 SOIC−8 D SUFFIX CASE 751 8 HEL52 ALYW G 1 1 1 8 HL52 ALYWG G 4Y M G G > 100 V Machine Model • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V