flip flop T Toggle
Abstract: flip flop T TOGGLE FLIP FLOP
Text: PSoC Creator Component Datasheet Toggle Flip Flop 1.0 Features • T input toggles Q value • Configurable width for array of Toggle Flip Flops General Description The Toggle Flip Flop captures a digital value that can be toggled. When to Use a Toggle Flip Flop
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MAX845ESA
Abstract: MAX845
Text: 19-0372; Rev 4; 10/97 KIT ATION EVALU E L B A AVAIL I sola t e d Tra nsform e r Drive r for PCM CI A Applic a t ions _Fe a t ure s ♦ Transformer Driver for Ultra-Thin 5V-µs Transformers The MAX845 consists of an oscillator followed by a toggle flip-flop. The flip-flop generates two 50% duty-cycle
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MAX845
450kHz,
MAX845EVKIT-MM)
159mm)
4732mm)
MAX845ESA
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ct109
Abstract: No abstract text available
Text: 74HC/HCT109 flip-flops D U A L JR FLIP-FLOP WITH SET A N D RESET; POSITIVE-EDGE TRIG G ER FEATURES T Y P IC A L J, K inputs fo r easy D -typ e flip-flop T oggle flip-flop o r " d o n o t h in g " m ode O u tp u t capability: standard IC C category: flip-flops
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74HC/HCT109
74HC/H
CT109
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Untitled
Abstract: No abstract text available
Text: f Z 7 S C S -T H O M S O N # & T 7 4 L S 1 12 A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP DESCRIPTION The T74LS112A is a dual JK flip-flop featuring in dividual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH,
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T74LS112A
T74LSe
T74LS112A
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100E531
Abstract: No abstract text available
Text: M M O T O R O L A Military 100E531 4-Bit D Flip-Flop Product Preview ELECTRICALLY TESTED PER: 100E531 T h e 100E531 is a quad m aster-slave D-type flip-flop with differential outputs. Each flip-flop m ay be clocked separately by holding Com mon Clock (C c ) LO W
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100E531
100E531
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TTL 74109
Abstract: 8530510 74109 PIN CONFIGURATION 74109
Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 0 9 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, S e t and R eset inputs; also com
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LS109A
74LS109A
33MHz
33MHz
70PULSE
500ns
500ns
1N916,
1N3064,
TTL 74109
8530510
74109
PIN CONFIGURATION 74109
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CP12A-1
Abstract: No abstract text available
Text: M MOTOROLA M ilitary 54LS112A D u a l J -K Flip-Flop W ith C le a r an d Pre se t ELECTRICALLY TESTED PER: MIL-M-38510/30103 The 54LS112A dual flip-flop features individual J, K, clock, and asyn chronous set and clear inputs to each flip-flop. When the clock goes
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MIL-M-38510/30103
54LS112A
54LS112A
JM38510/30103BXA
54LS112A/BXAJC
CP12A-1
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Flipflop t
Abstract: MC100EL35
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA J K Flip-Flop T he M C 1O EL/10 0E L3 5 is the m aster portion of the transferred to the slave, and the clock. Th e reset pin is HIGH. M C10EL35 M C100EL35 a high speed J K flip-flop. T h e J/K data enters flip-flop when the clock is L O W and is
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MC10EL/100EL35
525ps
C10EL35
C100EL35
DL140
Flipflop t
MC100EL35
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74LS113
Abstract: C0056
Text: 74LS113, S113 Signetics Flip-Flops Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. Th e asynchro nous S e t Sq input, w hen LOW , forces
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74LS113,
1N916,
1N3064,
500ns
500ns
74LS113
C0056
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R tm DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.
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DM74ALS109A
DM54ALS109A
LS109
D53-0
DM74ALS109AM
DM74ALS109AN
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A Military 10631 High Speed Dual D Type Master Slave Flip-Flop ELECTRICALLY TESTED PER: MIL-M-38510/06102 The 10631 is a dual master-slave type D flip-flop. Asynchronous Set (S) and Reset (R) override Clock (Cc) and Clock Enable (Cg) inputs. Each flip-flop may
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MIL-M-38510/06102
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74LS113
Abstract: No abstract text available
Text: 74LS113, S113 Flip-Flops S ig n e tics Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION TYPE T h e '1 1 3 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, S e t and Clock inputs. T h e asynchro nous S et Sp input, when LO W , forces
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74LS113,
500ns
500ns
1N916,
1N3064,
74LS113
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Untitled
Abstract: No abstract text available
Text: gl M O T O R O L A M C74AC109 M C 74A C T109 Dual J K Positive Edge-Triggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. T h ejtocking operation is independent of rise and fall
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C74AC109
MC74AC109/74ACT109
MC74AC74/74ACT74
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14013B
Abstract: No abstract text available
Text: H D 14013B Dual D -ty p e Flip Flop The HD14013B dual type D flip-flop has independent Data, D , Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip-flops for counter and toggle
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14013B
HD14013B
14013B
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98531
Abstract: F100131 F100331
Text: 100131 National Semiconductor F100131 T riple D Flip-Flop General Description The F100131 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Com mon Clock CPc , and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct
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F100131
F100131
F100331
TL/F/9853-8
TL/F/9853-10
98531
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Untitled
Abstract: No abstract text available
Text: f Z T SGS-THOMSON Ä T# HCC/HCF4013B IM E[HÎ(3 ilLi(OTM D(3S DUAL ’D' - TYPE FLIP-FLOP . SET-RESET CAPABILITY . STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINITELY WITH CLOCK LEVEL EITHER ’’HIGH” OR "LOW” • MEDIUM-SPEED OPERATION - 16MHz (typ.)
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HCC/HCF4013B
16MHz
100nA
HCC/HFC4013B
PLCC20
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Untitled
Abstract: No abstract text available
Text: *SYNERGY SY10EL51 SY100EL51 DIFFERENTIAL CLOCK D FLIP-FLOP SEMICONDUCTOR DESCRIPTION FEATURES • 475ps propagation delay T he SY10/100EL51 are differential clock D flip -flop s with reset. T hese devices are fun ction a lly sim ila r to the E151 devices, with higher perform ance capabilities. With
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SY10EL51
SY100EL51
475ps
SY10/100EL51
L51ZC
L51ZC
10OEL51ZCTR
T0013fl
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7473 pin diagram
Abstract: pin diagram of 7473 74LS73 pin diagram of ttl 7473 7473 dual JK TTL 74ls73 7473
Text: 7473, LS73 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION T h e '7 3 is a dual flip-flop with individual J, K, Clock and direct R eset inputs. The 7 4 7 3 is positive pulse-triggered. JK infor mation is loaded into the m aster while
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1N916,
1N3064,
500ns
500ns
7473 pin diagram
pin diagram of 7473
74LS73
pin diagram of ttl 7473
7473 dual JK
TTL 74ls73
7473
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16PIN
Abstract: 74F112 SOL16 TC74ACT112
Text: INTEGRATED T O SH IB A DUAL J - K TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 7 4 A C T 1 1 2P/F/FN DATA SILICON MONOLITHIC FLIP FLOP WITH PRESET AND CLEAR The TC74ACT112 is an advanced high speed CMOS DUAL JK FLIP FLOP fabricated with silicon gate and double - layer
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TC74ACT1
TC74ACT112
16PIN
DIP16-P-300A)
75MAX
735TYP
16PIN
200mil
OP16-P-300
74F112
SOL16
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74ls112 pin diagram
Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Text: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,
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1N916,
1N3064,
500ns
500ns
74ls112 pin diagram
74ls112 pin configuration
74LS112
N74S112D
74ls112 function table
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T112
Abstract: T-112
Text: INTEGRATED T O SH IB A DUAL J - K TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TECHNICAL T C 7 4 A C T 1 1 2P/F/FN DATA SILICON MONOLITHIC FLIP FLOP WITH PRESET AND CLEAR The TC74ACT112 is an advanced high speed CMOS DUAL JK FLIP FLOP fabricated with silicon gate and double - layer
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TC74ACT112
16PIN
16PIN
200mil
S0P16
705TYP
150mil
T112
T-112
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cd40138
Abstract: cd4013b CD4013 H R C M F 3B 334
Text: w Tex a s In s t r u m e n t s CD4013B Types D ata sheet acquired from Harris Sem iconductor S C H S023 CMOS Dual ‘D*-Type Flip-Flop Features: • Set-Reset capability ■ Static flip-flop operation — retains state indefinitely with clock level either
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CD401
4013B
13--Dynamic
CD4013BH
cd40138
cd4013b
CD4013
H R C M F 3B 334
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Untitled
Abstract: No abstract text available
Text: Philips Semiconductors-Signetics Document No. 853-0340 ECN No. 96144 Date of issue March 28.1989 Status Product Specification FAST 74F114 Flip-Flop Dual J-K Negative Edge-Triggered Flip-Flop With Common Clock And Reset FAST Products TYPE t y p ic a l ím a x
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74F114
N74F114
100MHz
74F114,
14-Pin
N74F114N
N74F114D
500ns
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54F109
Abstract: GDFP2-F16 GDIP1-T16 S54C
Text: P ro d u ct sp ecifica tio n P h ilip s S e m ic o n d u c to rs M ilitary F A S T P ro d u cts Flip-flop 54F109 Th e J K design allow s operation a s a D flip-flop by tying the J and K inputs together. DESCRIPTION Th e 54 F109 is a dual positive edge-triggered JK-type flip-flop
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54F109
500ns
7110flSb
GDFP2-F16
GDIP1-T16
S54C
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