FIFO BUFFER THRESHOLD Search Results

DLP-USB1

Contextual Info: DLP-USB1 DLP Design USB to FIFO Parallel Interface Module DLP-USB1 FEATURES Send / Receive Data over USB at up to 1 M Bytes / sec 384 byte FIFO Transmit buffer / 128 byte FIFO receive buffer for high data throughput Simple interface to CPU or MCU bus No in-depth knowledge of USB required as all USB

DLP-USB1

Abstract: USB1
Contextual Info: DLP-USB1 DLP Design USB to FIFO Parallel Interface Module DLP-USB1 FEATURES Send / Receive Data over USB at up to 1 M Bytes / sec 384 byte FIFO Transmit buffer / 128 byte FIFO receive buffer for high data throughput Simple interface to CPU or MCU bus No in-depth knowledge of USB required as all USB

LF3304QC12G

Abstract: LF3304
Contextual Info: LF3304 LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO Dual Line Buffer/FIFO DEVICES INCORPORATED FEATURES DESCRIPTION 100 MHz Data Rate for Video and other High-Speed Applications One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit

Contextual Info: LF3304 LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO Dual Line Buffer/FIFO DEVICES INCORPORATED FEATURES DESCRIPTION 100 MHz Data Rate for Video and other High-Speed Applications One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit

LF3304

Abstract: lf3304 i
Contextual Info: LF3304 LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO Dual Line Buffer/FIFO DEVICES INCORPORATED FEATURES DESCRIPTION 100 MHz Data Rate for Video and other High-Speed Applications One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit

Contextual Info: LF3304 LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO Dual Line Buffer/FIFO DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 100 MHz Data Rate for Video and other High-Speed Applications ❑ One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit

LF3304

Abstract: 15VZ
Contextual Info: LF3304 LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO Dual Line Buffer/FIFO DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 100 MHz Data Rate for Video and other High-Speed Applications ❑ One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit

LF3304

Abstract: BUFFER FIFO lf3304qc12
Contextual Info: LF3304 DEVICES INCORPORATED LF3304 Dual Line Buffer/FIFO Dual Line Buffer/FIFO DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 100 MHz Data Rate for Video and other High-Speed Applications ❑ One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit

fifo memory

Abstract: Avalon QII55002-7
Contextual Info: 4. On-Chip FIFO Memory Core QII55002-7.1.0 Core Overview The on-chip FIFO memory core is a configurable component used to buffer data and provide flow control in an SOPC Builder system. The FIFO can operate with a single clock or with separate clocks for the input

"7 Segment Display"

Abstract: common anode 7-segment display R8A66174SP m66300 HC138 HC373 PRSP0020DG-A R8A66160 R8A66174
Contextual Info: REJ03F0278-0101 Rev. 1.01 Oct.06.2008 R8A66174SP PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO DESCRIPTION The R8A66174 is a CMOS LSI with 63-byte FIFO First-In First-Out Memory . The commands or up to 63bytes data can be stored from 8-bit data bus. The data stored in FIFO can be outputted as serial data by

motorola D213 user guide

Abstract: SEMICONDUCTOR J601 eeprom u505 AD9226 J306 J307 J406 sine wave inverter schematic and firmware CR502 vr301 potentiometer
Contextual Info: High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALB FEATURES FUNCTIONAL BLOCK DIAGRAM Buffer memory board for capturing digital data used with high speed ADC evaluation boards to simplify evaluation 32 kB FIFO depth at 133 MSPS upgradable Measures performance with ADC Analyzer

AM7202

Abstract: am7202-25
Contextual Info: Advanced Micro Devices Am7202-25/35/50/65/80 CMOS First-In First Out FIFO 1024x9-Bit Buffer DISTINCTIVE CHARACTERISTICS • RAM based FIFO Status flags - full, half-full, empty • 1024x9 organization Retransmit capability • Cycle times of 35/45/65/80/100 nanoseconds

AM7203

Contextual Info: a Am7203-25/35/50/65/80 CM O S First-in First-out FIFO Advanced Micro Devices 2048x9-Bit Buffer DISTINCTIVE CHARACTERISTICS • RAM based FIFO • Status fla g * - full, half-full, empty • 2048x9 organization • Retransmit capability • Cycle times of 35/45/65/80/100 nanoseconds

Contextual Info: High Speed ADC USB FIFO Evaluation Kit HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC FEATURES FUNCTIONAL BLOCK DIAGRAM Buffer memory board for capturing digital data Used with high speed ADC evaluation boards 32 kB FIFO Depth at 133 MSPS upgradeable to 256 kB Simplifies evaluation of high speed ADCs

syn 7580

Abstract: 80960CA intel 8212 data sheet BSDE diode marking code 4n TPS 1028 1840H bicon TTL catalog Bt8215EPF
Contextual Info: Bt8215 Bidirectional Cell Buffer The Bt8215 Bidirectional Cell Buffer simplifies full-duplex communication between a 32-bit wide system bus and a 8-bit duplex peripheral bus. The buffer depth in each direction is 2048 bytes and can easily be expanded with off-theshelf FIFO parts. Special modes for buffering ATM cells are included.

AM7203

Contextual Info: H Advanced Micro Devices Am7201 -25/35/50/65/80 C M O S First-In First Out FIFO 512x9-Bit Buffer DISTINCTIVE CHARACTERISTICS • RAM baaed FIFO • Statu* flag« - full, half-full, empty • 512x9 organization • Retransmit capability • Cycle tim e* of 35/45/65/80/100 nanoseconds

AM7204

Abstract: 67C4502
Contextual Info: a P re lim in a ry Advanced Micro Devices Am7204-25/35/50/65/80 CMOS First-in First-out FIFO 4096x9-Bit Buffer DISTINCTIVE CHARACTERISTICS • RAM based FIFO • Status flag« - lull, halt-full, empty • 4096x9 organization • Retransmit capability • Cycle times of 35/45/65/80/100 nanoseconds

STK 4840

Abstract: stk 407 070 datasheet stk 407 070
Contextual Info: VSC7326 Datasheet FEATURES • • • • • • • • • • 12 x 10/100/1000 Mbps RGMII interfaces SPI-4.2 host interface with dynamic deskew 4032 kilobit ingress buffer, 1152 kilobit egress buffer 12-port wire-speed operation Store-and-forward and cut-through FIFO

M66300FP

Contextual Info: MITSUBISHI <DIGITAL ASSP> M66300P/FP PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO DESCRIPTION PIN CONFIGURATION TOP VIEW The M 66300P/FP is a C M O S -typ e la rg e -s c a le inte grated c irc u it w ith 63 -byte FIFO (F irs t-In F irst-O ut M e m o ry). C om ­

Am79C900

Abstract: be21 generator controller ILACC 506-200M-50
Contextual Info: PRELIM INARY a Am79C900 Integrated Local Area Communications Controller ILACC™ Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Integrated Ethernet controller and Serial Interface Adapter. On board 48-byte FIFO, DMA controller, and advanced buffer management scheme.

Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

LF3312

Abstract: LF3312BGC position sensitive diode circuit
Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

LF3312 m

Abstract: LF3312 LF3312BGC
Contextual Info: LF3312 12-Mbit Frame Buffer / FIFO DEVICES INCORPORATED Preliminary Datasheet Features 12,441,600-bit Frame Memory 74.25MHz Max Data Rate May be Organized Into the Following Configurations: • 1,555,200 x 8-bit single channel • 1,244,160 x 10-bit (single channel)

intel 8055

Abstract: BPK70 intel 7242
Contextual Info: in te i 7242 DUAL FORMATTER/SENSE AMPLIFIER FOR BUBBLE MEMORIES FIFO Data Block Buffer Error Detection/Correction Done Automatically Dual Channel Daisy-Chained Selects for Multiple Bubble Memory Systems On-Chip Sense Amplifiers MOS N-Channel Technology Automatically Handles Redundant