F676 Search Results

16-Blt

Contextual Info: 676 54F/F676 Connection Diagrams 16-Bit Serial/Parallel-ln, Serial-Out Shift Register Description The ’ F676 con tain s 16 flip -flo p s w ith provision fo r synchronous parallel or serial entry and serial ou tput. W hen th e Mode M input is HIGH, info rm atio n present on the parallel data (P0-P 15 ) in pu ts is entered on the

74F676SPC

Abstract: CERAMIC LEADLESS CHIP CARRIER 54F676DM 54F676SDM 74F676PC 74F676SC J24F M24B N24A N24C
Contextual Info: Semiconductor D ecem ber 1994 54F/F676 16-Bit Serial/Parallel-ln, Serial-Out Shift Register General Description Features The ’ F676 co ntains 16 flip-flo p s w ith provision fo r synchro­ nous parallel o r serial entry and serial output. W hen the M ode M input is HIGH, inform ation present on th e parallel

Contextual Info: O r*. (O a National Semiconductor 54F/F676 16-Bit Serial/Parallel-ln, Serial-Out Shift Register General Description Features The 'F676 contains 16 flip-flops with provision for synchro­ nous parallel or serial entry and serial output. When the Mode (M input is HIGH, information present on the parallel

Contextual Info: Nationa l Semiconductor MILITARY DATA SHEET Original Creation Date: 05/10/96 Last Update Date: 07/30/96 Last Major Revision Date: 05/10/96 F676-X REV 1A0 16-BIT SERIAL/PARALLEL— IN, SERIAL-OUT SHIFT REGISTER General Description The F676 contains 16 flip-flops with provision for synchronous parallel or serial entry

54F676

Abstract: 54F676DMQB 54F676FMQB 54F676LMQB M676
Contextual Info: MILITARY DATA SHEET Original Creation Date: 05/10/96 Last Update Date: 07/30/96 Last Major Revision Date: 05/10/96 F676-X REV 1A0 16-BIT SERIAL/PARALLEL-IN, SERIAL-OUT SHIFT REGISTER General Description The F676 contains 16 flip-flops with provision for synchronous parallel or serial entry

R13T

Contextual Info: <0 <0 National Semiconductor 54F/F676 16-Bit Serial/Parallel-ln, Serial-Out Shift Register General Description Features The 'F676 co ntains 16 flip-flo p s w ith provision fo r synchro­ nous parallel o r serial entry and serial output. W hen the M ode M input is HIGH, inform ation prese n t on th e parallel

Socket S1g1

Abstract: AMD Turion 64 Mobile Technology AM2 amd amd AM2 opteron pin package HTC B834 Socket S1g1 Processor Functional AMD SEMPRON 3000 socket 754 DIAGRAM SEMPRON Socket 754 AM2 31117 CMPXCHG16B
Contextual Info: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors Publication # 32559 Revision: 3.16 Issue Date: November 2009 2005-2009 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices,

54F676DM

Abstract: 54F676FM 54F676SDM 74F676 74F676PC 74F676SC 74F676SPC N24A N24C
Contextual Info: 54F F676 16-Bit Serial Parallel-In Serial-Out Shift Register General Description Features The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode M input is HIGH information present on the parallel

Contextual Info: ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x, F676x, MSP430F674x www.ti.com SLAS768D – SEPTEMBER 2012 – REVISED DECEMBER 2013 Polyphase Metering SoCs FEATURES 1 • 2 • • • • • • • • • • • • • •

MC68339

Abstract: 4 bit gray code synchronous counter wiring diagram using jk 732 LEM MC68836 937 motorola MC68840 MC68837 MC68838 SR1 B121 elm cst
Contextual Info: TABLE OF CONTENTS Paragraph Number Title Page Number Section 1 Introduction 1.1 1.2 1.3 Revision B Added Functionality .1-2

F199 transistor

Abstract: F46B F17E ST F445 d732 a9ca 34ba 8230C f451 F422
Contextual Info: National Semiconductor Application Note 486 Ashok Krishnamurthy April 1987 INTRODUCTION This report describes the implementation of a Single Precision Floating Point Arithmetic package for the National Semiconductor HPC microcontroller The package is based

74F161 PC

Abstract: 74F163PC 74f500 74f558 74F164PC 74F548PC 74F138d 74F547PC transistor f630 74F253DC
Contextual Info: F a ir c h ild A d v a n c e d S c h o t t k y T L $ 3. HANDLING PRECAUTIONS FOR SEMICONDUCTOR COMPONENTS The follow ing handling precautions should be observed for oxide isolation, shallow junction processed parts, such as FAST or 100K ECL: 1. All Fairchild devices are shipped in conducting foam or anti­

12F676

Abstract: 6B24 5B30
Contextual Info: ispMACH 5000VG Family TM 3.3V In-System Programmable SuperBIG, SuperWIDE High Density PLDs TM TM December 2001 Data Sheet • Ease of Design Features • Product term sharing • Extensive clocking and OE capability ■ High Density • 768 to 1,024 macrocells

amd x4 630

Abstract: AMD BIOS KERNEL STR W 5453 A regulator B834 A934 transistor a934 Chipkill developer 8259 PIC A934 transistor AMD athlon socket 754
Contextual Info: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors TM TM Publication # 26094 Revision: 3.06 Issue Date: September 2003 2002, 2003 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices,

Contextual Info: MSP430F677x1, F676x1, MSP430F674x1 www.ti.com SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013 Polyphase Metering SoCs FEATURES 1 • 2 • • • • • • • • • • • • • • • • • • Accuracy < 0.1% Over 2000:1 Dynamic Range

Contextual Info: MSP430F677x1, F676x1, MSP430F674x1 www.ti.com SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013 Polyphase Metering SoCs FEATURES 1 • 2 • • • • • • • • • • • • • • • • • • Accuracy < 0.1% Over 2000:1 Dynamic Range

Contextual Info: Preliminary a Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 • ■ Repeat Filter ■ Hardware Physical Connection Management (PCM) support ■

Contextual Info: MSP430F677x1, F676x1, MSP430F674x1 www.ti.com SLAS815C – NOVEMBER 2012 – REVISED DECEMBER 2013 Polyphase Metering SoCs FEATURES 1 • 2 • • • • • • • • • • • • • • • • • • Accuracy < 0.1% Over 2000:1 Dynamic Range

Contextual Info: M0-?;G7CD3=0!?AFE03F070CF.4 M0 @H7C035E@C0@CC75E76 M0@?G75E;@?0@@=76 M0F0J73C0H3CC3?EJ M0@>A35E07D;9? *<0&60*80 *,2*387020551.(&8.437 35E@CJ0FE@>3E;@? ,7DE020%73DFC7>7?E $;9:E0!?6FDEC;3=0BF;A>7?E 2/+70+7C;7D FA/0E@0BFA/0+;?9=70'FEAFE0(@H7C0+FAA=;7D60

Contextual Info: FVeliminaiy n Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 • Line state detection ■ ■ Hardware Physical Connection Management (PCM) support

NP920

Abstract: SUPERNET 2 Family pcms AM79C864A NP10 AMD Supernet am79864a AMD Supernet 2 NP5-12 NP1223
Contextual Info: PRELIMINARY Am79C864A Physical Layer Controller With Scrambler PLC-S Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 ■ Line state detection ■ Implements ANSI standard Stream Cipher

Contextual Info: Semiconductor December 1994 54F/F676 16-Bit Serial/Parallel-ln, Serial-Out Shift Register General Description Features The ’F676 contains 16 flip-flops with provision for synchro­ nous parallel or serial entry and serial output. When the Mode M input is HIGH, information present on the parallel

Contextual Info: ECCN 5E002 TSPA - Technology / Software Publicly Available MSP430F677x F676x MSP430F674x www.ti.com SLAS768B – SEPTEMBER 2012 – REVISED JANUARY 2013 POLYPHASE METERING SoCs FEATURES 1 • • • • • • • • • • • • • • • •

020H-021H

Abstract: SLAS815B
Contextual Info: MSP430F677x1 F676x1 MSP430F674x1 www.ti.com SLAS815B – NOVEMBER 2012 – REVISED APRIL 2013 POLYPHASE METERING SoCs FEATURES 1 • • • • • • • • • • • • • • • • Accuracy < 0.1% Over 2000:1 Dynamic Range for Phase Current