F1013 Search Results

F10132

Abstract: F10532
Contextual Info: F10132 • F10532 DUAL MULTIPLEXER/LATCH h QnnaratoT h F1° 132 and F10532 are dual m ultiplexers w ith D type latches !? S° lect and Reset i nP“ ts. Each latch may be enabled “ LOGIC SYMBOL In a b « f p 'u n n i fl*K ^ 0n Enable <Ec) in ,he LOW sta,e or bV using the

F10135

Abstract: F10535 fairchild ECL
Contextual Info: F10135~* F 1 0 5 3 5 ^ F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled Flip­ Flop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

WR112 5W Load

Contextual Info: P B tiG E C p l e s s e y DS3536-1.1 F1013-49 & F1147/48 LOW POWER WAVEGUIDE CIRCULATORS * FREQUENCY COVERAGE 7.75 - 40.0GHz * CIRCULATORS AND ISO-CIRCULATORS AV A ILA B LE * 4-PORT VERSIONS IN R120 & R140 * COMPACT AND ROBUST CONSTRUCTION This data sheet describes a standard range of 3-port circulators and iso-circulators in R84, R100,

Contextual Info: EDD H br D15D20 TITLE F E D C B A REV 11/10/11 1/14/08 1/14/08 10/30/07 10/09/07 2/28/07 02/17/04 DATE SP MCS MCS MCS MCS AWM ALM BY REVISION 11-1238 08/F0015 NO CHANGE 07-F1088 07-F1013 07-F0187 07-F0187 EN NUMBER INC. INC. 8851 SW OLD KANSAS AVE STUART, FL 34997

bcd counter using j-k flip flop diagram

Abstract: pn sequence generator using jk flip flop F10136 ECL Handbook
Contextual Info: / / / F10136 • F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/FI 0537 are 4-stage synchronous counters capable of operating at typical count rates of 250 MHz. The circuits are designed

12J2

Abstract: 1.2j2 F10535 F10135
Contextual Info: F10135^ F10535 F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled FlipFlop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

Contextual Info: POLYFET R F DEVICES SbE D • 724100^ 0000052 fl ■ 7\39’09 POLYFET RF DEVICES F1013 PATENTED GOLD METALIZED SILICON RF POWER MOSFET General Description Silicon vertical DMOS designed specifically for RF applications. Immune to forward and reverse bias secondary breakdown.

Contextual Info: F10135 • F10535 F10K VOLTAGE COMPENSATED ECL DUAL JK FLIP-FLOP DESCRIPTION - The F10135 and F10535 are Dual Master/Slave DC Coupled FlipFlop. Asynchronous Clear Direct CD and Set Direct (SD) are provided and override the clock. The output states of each flip-flop change on the LOW to HIGH transition of

si117

Contextual Info: F10136 • F10536 • F10137 • F10537 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10136/F10536 and F10137/F10537 are 4-stage synchronous counters capable of operating at typical count rates ot 250 MHz. The circuits are designed

F10130

Abstract: F10530
Contextual Info: F10130 • F10530 DUAL D LATCH DESCRIPTION - The F10130/F10530 contains_a pair of D type latches with a Common Enable Ec input. Each latch has its own Enable (En), Set (S) and ResetJR) inputs. For each latch, the data present on the D input appears on the Q output when both En and Ec are LOW,

F10133

Abstract: F10533
Contextual Info: F10133 • F10533 QUAD LATCH DESCRIPTION — The F10133 and F10533 are high-speed low power Quad Latches consisting of four bistable latch circuits with D type inputs and gated outputs. Open em itters allow a large number of o utputs to be wired-OR together and latch

Contextual Info: F 10134^» F10534^ DUAL MULTIPLEXER/LATCH DESCRIPTIO N — The F10134 and F10534 are Dual Multiplexers with D type latches. Each latch may be enabled separately by holding the Common Enable in the LOW state and using the Enable En inputs. If the Com mon Enable (Ec) is used to enable the latch,

fairchild ECL

Abstract: F10137 F10136 F10536 F10537 ECL Handbook 125-250MHz
Contextual Info: F10136^ F10536 • F10137 • F10537 V 4-STAGE UP/DOWN COUNTERS F10K VOLTAGE COMPENSATED ECL D ESCRIPTIO N - The F10136/F10536 and F10137/F10537 are 4-stage synchronous counters capable o f operating at typical count rates of 250 MHz. The circuits are designed

logic diagram

Abstract: F10134 F10534
Contextual Info: F 1 0 1 3 4 ^ F 1 0 5 3 4 ^ DUAL MULTIPLEXER/LATCH DESCRIPTION — The F10134 and F10534 are Dual Multiplexers with D type latches. Each latch may be enabled separately by holding the Common Enable in the LOW state and^jsing the Enable En inputs. If the Common Enable (E c ) is used to enable the latch

743 LEM

Contextual Info: F10131 • F10531 HIGH SPEED DUAL D FLIP-FLOP DESCRIPTION - The F10131/F10531 contains two master/slave D-type flip-flops. The internal clock is the O R of two dock inputs, one common to both flip-flops. The O B clock permits the use of one input as a clock pulse and the other as an active LO W enable. While the

Contextual Info: F10133 • F10533 QUAD LATCH DESC RIPTIO N— The F10133 and F10533 are high-speed low power Quad Latches consisting of four bistable latch circuits with D type inputs and gated outputs. Open em itte rs a llow a large number of o u tpu ts to be wired-OR together and latch

Contextual Info: F10133 • F10533 QUAD LATCH DESCRIPTION — The F10133 and F10533 are high-speed low power Quad Latches consisting of four bistable latch circuits with D type inputs and gated outputs. Open em itters a llow a large number of o utputs to be wired-OR together and latch

Contextual Info: F10130* F10530 DUAL D LATCH DESCRIPTION - The F10130/F10530 contains_a pair of D type latches with a Common Enable Ec input. Each latch has its own Enable (En), S et (S) and ResetJR ) inputs. For each latch, the data present on the D input appears on the Q output when both En and Ec are LOW,

Contextual Info: F10132 • F10532 DUAL MULTIPLEXER/LATCH DESCRIPTION — The F10132 and F10532 are dual multiplexers with D type latches and have common Data Select and Reset Jnputs. Each latch may be enabled separately by holding the Common Enable Ec in the LOW state or by using the

U214D

Contextual Info: F 1 0 1 3 1 ^ F 1 0 5 3 1 ^ HIGH SPEED DUAL D FLIP-FLOP DESCRIPTION - The F10131/F10531 contains two master/slave D-type flip-flops. The internal clock is the OR of two clock inputs, one common to both flip-flops. The OR clock permits the use of one input as a clock pulse and the other as an active LOW enable. While the

CPIE

Abstract: F10131 F10531 fairchild ECL
Contextual Info: F 10131^ F 10531 ^ HIGH SPEED DUAL D FLIP-FLOP DESCRIPTION - The F10131/F10531 contains two master/slave D-type flip-flops. The internal clock is the OR of two clock inputs, one common to both flip-flops. The OR clock permits the use of one input as a clock pulse and the other as an active LOW enable. While the

Contextual Info: F10134 • F10534 DUAL MULTIPLEXER/LATCH DESCRIPTION— The F10134 and F10534 are Dual Multiplexers with D type latches. Each latch may be enabled separately by holding the Common Enable in the LOW state and using the Enable En inputs. If the Common Enable(Ec) is used to enable the latch,

LT 741 S

Contextual Info: F10130 • F10530 DUAL D LATCH DESCRIPTION - The F10130/F10530 contains_a pair of D type latches with a Common Enable Ec input. Each latch has its own Enable (En), Set (S) and Reset^R) inputs. For each latch, the data present on the D input appears on the Q output when both En and Ec are LOW,

maxim max8770

Abstract: wpc8763ldg varistor k11 k17 SM 630 finger print module PCI7412 040 U3D 78L12 WPC8763L BCM5787MKMLG 1D05V
Contextual Info: A B C D Biwa Block Diagram Project code: 91.4H001.001 PCB P/N : 55.4H001.XXX REVISION : 06237-3 GCE, Hannstar Mobile CPU CLK GEN. 4 Merom 479 2G/2.33G ICS 9LPR502 (RTM875T-605) 3 2.0G : B0, QLYV 2.2G : B0, QLFS E 4 -3-0313 G792 20 PCB STACKUP 4, 5 TOP CPU DC/DC