ERASABLE PROGRAMMABLE LOGIC DEVICE 610 Search Results

1B60

Abstract: PEEL programming msi ms 1772
Contextual Info: AMI PEEL 173 SEMICONDUCTORS CM O S Programmable Electrically Erasable Logic Device February 1993 Features General Description FPLA Architecture The AMI PEEL173 is a CMOS Programmable Electrically Erasable Logic device that provides a high-performance, low-power,

Contextual Info: fax id: 6102 CY7C343 CY7C343B 64-Macrocell MAX EPLD Functional Description Featu res • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array The CY7C343/CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin

ATV2500c

Abstract: ATF2500C programming
Contextual Info: Features • • • • • • • • • • • High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 10 ns Maximum Pin-to-pin Delay for 5V Operation Low-power Edge-sensing “L” Option with <1 mA Standby Current

ATV2500c

Contextual Info: Features • • • • • • • • • • • High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 10 ns Maximum Pin-to-pin Delay for 5V Operation Low-power Edge-sensing “L” Option with <1 mA Standby Current

TEA1

Contextual Info: Features • • • • • • • • • • • High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 10 ns Maximum Pin-to-pin Delay for 5V Operation Low-power Edge-sensing “L” Option with <1 mA Standby Current

EP610PC-35

Abstract: ep610di EP610DC-25 EP610DC-30 EP610LI EP610LC30 16 macrocell EP610PC EP610PC-30 EP610-30
Contextual Info: EP610 HIGH-PERFORMANCE 16-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3177, OCTOBER 1988—AUGUST 1989 • High-Density (Over 600 Gates) Replacement for TTL and 74HC DUAL-IN-LINE PACKAGE (TOP V IE W ) • Virtually Zero Standby Power . . . Typ 20 pA

EP910PC-40

Abstract: EP910PC-30 EP910LC-30 bit 3501 Architecture EP910DC-40 EP910LI PACKAGE EP910DC-30 EP910 24-MACROCELL EP910DC
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187, OCTOBER 1988 —REVISED AUGUST 1&89 DUA L-IN-LINE PACKAGE • High-Density (Over 900 Gates) Replacem ent for TTL and 74H C • Virtually Zero Standby P o w e r. . . Typ 20 |iA

EP610PC-25

Abstract: EP610PC-30 16-MACROCELL EP610DC-25 EP610LI EP610PC-35 Erasable Programmable Logic Device EP610LC-30 EP610 EP610PC
Contextual Info: EP610 HIGH-PERFORMANCE 16-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3177, OCTOBER 1988-AUGUST 1989 • High-Density (Over 600 Gates) Replacement for TTL and 74HC DUAL-IN-LINE PACKAGE (TOP VIEW) • Virtually Zero Standby P ow er. . . Typ 20 pA C 1 ^ 2 4 3 vcc

EP910PC-30

Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA

27C400 eprom

Abstract: 27C400 tms27c400 K1631 27PC40
Contextual Info: TMS27C400 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC400 4 194 304-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS400A-OCTOBER 1992-REVISED JANUARY 1993 Word-Wide 256K x 16 or Byte-Wide (512K x 8) Configurable 4-Megablt Mask ROM Compatible - 40-Lead CERDIP Package

27pc256

Abstract: 27e256 tms jl 27C256-15 27PC256NL TMS27C256 Bipolar PROM texas instrument 27PC256-1 TMS27C256-XXX 27c256-15 TEXAS INSTRUMENTS ti 27c256
Contextual Info: TMS27C256 2 6 2 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY S M L S 2 5 6F -S E P T E M B E R 198 4-R E V IS E D JA NUA RY 1993 This Data Sheet is Applicable to A ll TMS27C256S and TMS27PC256S Symbolized with Code “B " as Described

TTL 7400

Abstract: CY7C342 7400 datasheet ttl gate 7400 series CMOS Logic ICs 7400 series logic ICs 7400 TTL datasheet CY7C342B 7400series ttl cmos logic 7400 series
Contextual Info: This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the CY7C342B. 1CY 7C34 2 fax id: 6103 CY7C342 128-Macrocell MAX EPLDs Features • • • • • 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins

texas ic 6116

Contextual Info: TMS27C512 524.288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC512 524,288 BIT PROGRAMMABLE READ-ONLY MEMORY N O VEM BER 1985 - This Data Sheet is Applicable to AH TMS27C512s and TMS27PC512s Symbolized w ith Code "A " as Described on Page 12. J AND N PACKAGE

tms27pc256

Abstract: cm2 5612 TMS27C256JL S27C256 FML 612
Contextual Info: TMS27C256 262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC256 262 144-BIT PROGRAMMABLE READ-ONLY MEMORY REVA SMLS256E - SEPTEMBER 1964 This Data Sheet is Applicable to All TMS27C256S and TMS27PC256s Symbolized with Code “B" as Described on Page 7-25.

7400 series logic ICs

Abstract: CY7C341 CY7C341B
Contextual Info: fax id: 6105 1CY 7C34 1 This is an abbreviated data sheet. Contact a Cypress Representative for complete specifications. For new designs please refer to the CY7C341B. CY7C341 192-Macrocell MAX EPLD Features • • • • • • 92 macrocells in 12 LABs

27c291

Abstract: 27C292 27C292-5 TMS27C292 27C291-45 TMS27C291 27C291-3 27C291-50 27PC291 27C2923
Contextual Info: TMS27C291, TMS27C292 16,384-BIT UV ERASABLE PROGRAMMABLE READ ONLY MEMORIES TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEMBER 1986-R EV ISED APRIL 1988 Organization . . . 2K x 8 J AND N PACKAGE TOP VIEW Single 5-V Power Supply All Inputs/Outputs TTL Compatible

tms jl 27C512

Abstract: TMS27C512JE SMJ27C
Contextual Info: TMS27C512 524,288-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PCS12 524,288-BIT PROGRAMMABLE READ-ONLY MEMORY 0 D 7 7 S 1 ? fl 'N O VEM B ER 1985 - REVISED APRIL 1988 J AND N PACKAGE T - t/ 6 * / 3 mZ $ ‘ TOP VIEW T ~ y é '/ 3 '¿ f A 1 5 C 1 1J 2 8 □ v c c

27C256-16

Abstract: tms jl 27c256-12
Contextual Info: • fllk lT SS 0 0 7 7 2 0 3 â ■ TMS27C256 262,144BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC2S6 262,144 BIT PROGRAMMABLE READ-ONLY MEMORY TEXAS INSTR ASIC/MEMORY 25E D SEPTEMBER 1964—revised march 19sb This Data Sheet is Applicable to AH

2956

Abstract: 1065002 MN170
Contextual Info: TMS28F010A 1048576-BIT FUSH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY SM JS012-DECEM BER 1992-R E V IS E D NOVEMBER 1993 N PACKAGE O rganization. . . 128K x 8-Bit Flash Memory Pin Com patible W ith Existing 1-Megabit EPROMs V q c Tolerance ±10%

12950-012a

Abstract: pal 007a si 13003 al 13003 pal 005a 13003 application notes pal 003A pal 010a 13003 circuit 13003 d
Contextual Info: COM’L: H-15/25 MIL: H-20 PALCE610 Family Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: COM’L: H-15/25 MIL: H-20 Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: COM’L: H-15/25 MIL: H-20 H Advanced Micro Devices PALCE610 Family EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture ■ Asynchronous clocking via product term or bank register clocking from external pins

Contextual Info: COM’L: H-15/25 MIL: H-20 SI PALCE610 Family Advanced Micro Devices EE CMOS High Performance Programmable Array Logic DISTINCTIVE CHARACTERISTICS • AMD’s Programmable Array Logic PAL architecture Asynchronous clocking via product term or bank register clocking from external pins

CY7C341B

Abstract: CY7C341
Contextual Info: fax id: 6106 1CY 7C34 1B CY7C341B 192-Macrocell MAX EPLD Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms