ELPIDA DLL CIRCUIT Search Results

C10A

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442- C10A, 45D128842- C10A, 45D128164- C10A 128 M-bit Synchronous DRAM with Double Data Rate 4-bank, SSTL_2 Description The µPD45D128442-C10A, 45D128842-C10A, 45D128164-C10A are high-speed 134,217,728 bits synchronous

elpida DLL circuit

Abstract: elpida ELPIDA ddr2 chip EDE2108AASE
Contextual Info: PRELIMINARY DATA SHEET 2G bits DDR2 SDRAM EDE2104AASE 512M words x 4 bits EDE2108AASE (256M words × 8 bits) Description Features The EDE2104AASE is a 2G bits DDR2 SDRAM organized as 67,108,864 words × 4 bits × 8 banks. The EDE2108AASE is a 2G bits DDR2 SDRAM

elpida DLL circuit

Abstract: elpida EDE2108
Contextual Info: PRELIMINARY DATA SHEET 2G bits DDR2 SDRAM EDE2104AASE 512M words x 4 bits EDE2108AASE (256M words × 8 bits) Description Features The EDE2104AASE is a 2G bits DDR2 SDRAM organized as 67,108,864 words × 4 bits × 8 banks. The EDE2108AASE is a 2G bits DDR2 SDRAM

uPD45D128164G5-C75-9LG

Abstract: uPD45D128442G5-C75-9LG uPD45D128442G5-C80-9LG uPD45D128842G5-C75-9LG uPD45D128842G5-C80-9LG
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442, 45D128842, 45D128164 128 M-bit Synchronous DRAM with Double Data Rate 4-bank, SSTL_2 Description The µPD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2516AKTA 16M words x 16 bits Description Pin Configurations The EDD2516AK is a 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at

DDR400

Abstract: BT122
Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5 32M words x 8 bits, DDR400 EDD2516AMTA-5 (16M words × 16 bits, DDR400) Pin Configurations The EDD2508AMTA-5 is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AMTA-5 is a 256M bits

AX12

Abstract: DDR400 DDR400B
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508ARTA-5B 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508ARTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at

EDD2516AMTA-6B-E

Abstract: auto-10
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516AMTA-6B-E 16M words x 16 bits Description Pin Configurations The EDD2516AMTA is 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for

AX12

Abstract: DDR400 DDR400B BT122
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508ARTA-5B 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508ARTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at

BT122

Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516ARTA-6B 16M words x 16 bits Specifications Pin Configurations • Density: 256M bits • Organization  4M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) • Power supply: VDD, VDDQ = 2.5V ± 0.2V

AX12

Abstract: DDR400 DDR400B BT122
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5B-E 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508AMTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at

AX12

Abstract: DDR400 DDR400B BT122
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5B-E 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508AMTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at

EDD2516AMTA-6B-E

Abstract: BT122
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516AMTA-6B-E 16M words x 16 bits Description Pin Configurations The EDD2516AMTA is 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for

BT122

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA 32M words x 8 bits EDD2516AMTA (16M words × 16 bits) Description Pin Configurations The EDD2508AM is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AM is a 256M bits DDR

BT122

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA 32M words x 8 bits EDD2516AMTA (16M words × 16 bits) Pin Configurations The EDD2508AM is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AM is a 256M bits DDR

DDR400

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5 32M words x 8 bits, DDR400 EDD2516AMTA-5 (16M words × 16 bits, DDR400) Description Pin Configurations The EDD2508AMTA-5 is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8

Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232AABH-5 4M words x 32 bits, DDR400 Description Features The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232AABH-5 4M words x 32 bits, DDR400 Description Features The EDD1232AA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

DDR400

Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516AKTA-5-E 16M words x 16 bits, DDR400 Description Pin Configurations The EDD2516AKTA-5 is a 256M bits DDR SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross

DDR400

Abstract: EDD1232AAFA-5C-E
Contextual Info: PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1232AAFA-5 4M words x 32 bits, DDR400 Description Features The EDD1232AA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232AAFA-5 4M words x 32 bits, DDR400 Description Features The EDD1232AAFA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AKTA-5-E 32M words x 8 bits, DDR400 Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 8M words × 8 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant)

EDD1232ABBH

Abstract: EDD1232ABBH-5C-E
Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232ABBH 4M words x 32 bits Specifications Features • Density: 128M bits • Organization ⎯ 1M words × 32 bits × 4 banks • Package: 144-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.125V

DDR400B

Contextual Info: DATA SHEET 128M bits DDR SDRAM EDD1232ACBH 4M words x 32 bits Specifications Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: 144-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 2.5V −0.125V/+0.2V