ELECTRICAL CHARACTERISTICS OF 8096 Search Results

Contextual Info: 80960HA/HD/HT 1.0 ABOUT THIS DOCUMENT This document provides a preview of Intel’s 80960Hx embedded superscalar microprocessors. Future revisions of this document will provide targeted electrical characteristics. Detailed descriptions for functional topics — other than parametric perfor­

8096 processor architecture

Contextual Info: intei 1.0 8 0 9 6 0 H A/H D / H T This docum ent provides a preview of Intel’s 80960Hx embedded superscalar microprocessors. Future revisions of this docum ent will provide targeted electrical characteristics. Detailed descriptions for functional topics — other than param etric perfor­

branch conditional unconditional instruction

Abstract: 80960CF Intel 960
Contextual Info: 80960CF-40, -33, -25, -16 1.0 PURPOSE 2.0 This document provides electrical characteristics of Intel's ¡960 CF embedded microprocessor. For functional descriptions consult the /'960® Cx Micro­ processor User’s Manual 270710 . To obtain data sheet updates and errata, contact Intel at any of the

80960CF

Abstract: Q1730 80960CA 80960CF-33 80960CF-40 FCX-04 fcx-02 CX020A til 701
Contextual Info: intèi 1.0 80960CF-40, -33, -25, -16 PURPOSE 2.0 This document provides electrical characteristics of Intel’s i960 CF embedded microprocessor. For functional descriptions consult the i96 P Cx Micro­ processor User's Manual (270710 . To obtain data sheet updates and errata, contact Intel at any of the

i486 sx

Abstract: 80960CX 80960JF 80960RD 80960RP 272736 272918 INTEL386 pipeline architecture
Contextual Info: Intel i960® RX I/O Processor at 3.3 Volts Datasheet • 33 MHz, 3.3 Volt Version 80960RP 33/3.3 • 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core • Complies with PCI Local Bus Specification, Revision 2.1 • 5 Volt PCI Signalling Environment

80960Cx

Abstract: PCI80960 80960JF 80960RP i960RP
Contextual Info: Intel i960® RP I/O Processor Datasheet • 33 MHz, 5 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification, Revision 2.1 Product Features • ■ ■ ■ ■ High Performance 80960JF Core —Sustained One Instruction/Clock Execution

am3 socket pin diagram

Abstract: gc80303 socket AM2 pinout socket am3 pinout differential relay 273358 PAD45
Contextual Info: Intel 80303 I/O Processor •66 MHz PCI-to-PCI Bridge MHz SDRAM and Internal Bus ■Complies with PCI Local Bus Specification, Revision 2.2 ■Universal 5 V and 3.3 V PCI Signaling Environment ■100 Datasheet Product Features ■ ■ ■ ■ High Performance 100 MHz Intel® 80960JT

QFP PACKAGE thermal resistance

Abstract: 80960SA 80960SB N80960SB1 65A176 AD928
Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture ■ Built-in Interrupt Controller — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ 512-Byte On-Chip Instruction Cache

Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

80960SA

Abstract: 80960SB 65A176 272206-003
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

80960SA

Abstract: 80960SB 65A176 AD427
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache

intel packaging handbook 240800

Abstract: 25809 80960JA 80960JD 80960JF 27248
Contextual Info: A PRELIMINARY 80960JA/JF EMBEDDED 32-BIT MICROPROCESSOR • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers

Non-Pipelined processor

Abstract: 80960CF 80960CA intel packaging handbook 240800 80960CF-33 80960CF-40 Non-Pipelined Single-Cycle processor 270710
Contextual Info: A PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • ■ ■ ■ ■ ■ • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining

advantages of instruction set architecture intel i3

Contextual Info: 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • H ig h -P e rfo rm a n c e E m bedded A rc h ite c tu re — 16 M IPS* B u rst E xecution at 16 M H z — 5 M IPS S u stain ed E xecution at 16 M Hz ■ B uilt-in In te rru p t C o n tro lle r

T7 DIODE

Contextual Info: inttJ PBßyiiflOMÄlHV 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

80960RP

Abstract: Intel Order Intel 960
Contextual Info: iniol 1.0 80960 RP ABOUT THIS DOCUMENT 1.2 This data sheet contains ADVANCE INFORMATION about Intel’s ¡960 RP processor, including a func­ tional overview, m echanical data package signal locations and sim ulated thermal characteristics , targeted electrical specifications (simulated), and

Contextual Info: in te l 80960JA /JF EMBEDDED 32-BIT MICROPROCESSOR • Pin/Code Compatible with all 80960Jx Processors ■ High-Performance Embedded Architecture — One Instruction/Clock Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers 8

VAX-11

Abstract: PLCC 68 intel package dimensions 270917 w1a31 intel core i7 processors their registers in term of 32-bit mode
Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

VAX-11

Abstract: 272207
Contextual Info: in t t J P ß m oM ow A nv 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

82961KA

Abstract: canon pinout cartridge printer video board "canon " printer
Contextual Info: P e ® y T [FiraEWQQ in t e i 82961KA PAGE PRINTER CONTROLLER High Integration i960® Page Printer Controlled1 — Direct Interface to 32-bit 80960KA or KB<2) Embedded Processors Direct Non-Impact Printer Video Interface — Automatic DMA Burst DRAM Access

80960CA-33

Abstract: ALI 3105 80960CA 80960CA-25 FCX-03
Contextual Info: 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture ■ ■

80960c

Abstract: 80960CF 80960CA 80960CF-33 80960CF-40 272886 270710
Contextual Info: 80960CF-40, -33, -25 32-Bit High-Performance Superscalar Embedded Microprocessor Datasheet Product Features • ■ ■ ■ Socket and Object Code Compatible with 80960CA Two Instructions/Clock Sustained Execution Four 71 Mbytes/s DMA Channels with Data Chaining

Contextual Info: 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • • Two Instructions/Clock Sustained Execution Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution