EEPROM LOGIC 1997 Search Results

Siemens SLE

Abstract: Mifare mikron 44C42 Mifare reader protocol mikron 4K Mifare CMS Semiconductor
Contextual Info: ICs for Chip Cards SLE 44R42S "Combi Card-IC" 8-bit Security Controller with 17-Kbyte ROM, 256-byte RAM, 4-Kbyte EEPROM and Sleep Mode combined with MIFARE -Circuit for Contactless Transmission with Security Logic and Anti-Collision and 4-Kbyte Common-EEPROM

10-SPEED

Abstract: RQFP EPM9400A
Contextual Info: MAX 9000A Programmable Logic Device Family April 1997, ver. 1 Features Advance Information Brief • ■ Advanced Information ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

PQFP 256

Abstract: 256-pin BGA
Contextual Info: Michelangelo Programmable Logic Device Family May 1997, ver. 2 Features Advance Information Brief • ■ Advance Information ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on fourth-generation Multiple Array MatriX

337 BGA footprint

Abstract: 153G8 three d flipflop chip EPM7032B EPM7064B EPM7128B EPM7256B EPM7256E EPM7512B JESD-71
Contextual Info: MAX 7000B Programmable Logic Device Family October 2000, ver. 2.1 Data Sheet • Features. Preliminary Information ■ f High-performance 2.5-V CMOS EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)

C732B

Abstract: 337 BGA 337 BGA footprint EPM7032AE EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE
Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family August 2000, ver. 3.1 Data Sheet • Features. ■ ■ ■ ■ ■ ■ ■ f High-performance 3.3-V EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

eeprom programmer schematic

Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family June 1999, ver. 2.01 Data Sheet Features. • ■ Preliminary Information ■ ■ ■ ■ ■ f High-performance CMOS EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

EPM7218

Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family July 1999, ver. 2.02 Data Sheet Features. • ■ Preliminary Information ■ ■ ■ ■ ■ f High-performance CMOS EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

TTL pin outs

Abstract: 30J341 CMOS TTL Logic Family Specifications BGA and QFP Package BITBLASTER footprint tqfp 208 v16 248 337 BGA footprint N12110 74 series pin outs
Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family September 1999, ver. 2.03 Data Sheet Features. • ■ Preliminary Information ■ ■ ■ ■ ■ f High-performance CMOS EEPROM-based programmable logic devices PLDs built on second-generation Multiple Array MatriX

epm7032

Abstract: EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E K2107
Contextual Info: Includes MAX 7000E & MAX 7000S MAX 7000 Programmable Logic Device Family July 1999, ver. 6.01 Features. Data Sheet • ■ ■ ■ ■ ■ ■ f High-performance, EEPROM-based programmable logic devices PLDs based on second-generation Multiple Array MatriX (MAX®)

EPM7192S

Abstract: EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E epm7064 adapter MAX7000E
Contextual Info: Includes MAX 7000E & MAX 7000S MAX 7000 Programmable Logic Device Family August 2000, ver. 6.02 Features. Data Sheet • ■ ■ ■ ■ ■ ■ f High-performance, EEPROM-based programmable logic devices PLDs based on second-generation Multiple Array MatriX (MAX®)

100-Pin Package Pin-Out Diagram

Abstract: 7128s 84-Pin Package Pin-Out Diagram CLASSIC EPLD FAMILY u8318 EPM7064 100-Pin Package Pin-Out Diagram
Contextual Info: Includes MAX 7000E & MAX 7000S MAX 7000 Programmable Logic Device Family June 1996, ver. 4 Data Sheet Features. • ■ ■ ■ ■ ■ ■ ■ ■ High-performance, EEPROM-based programmable logic devices PLDs based on second-generation Multiple Array MatriX (MAX)

EPM9560 pinout

Contextual Info: MAX 9000 Programmable Logic Device Family June 1996, ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

D2433

Abstract: EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E 100-Pin Package Pin-Out Diagram
Contextual Info: Includes MAX 7000E & MAX 7000S MAX 7000 Programmable Logic Device Family July 1999, ver. 6.01 Features. Data Sheet • ■ ■ ■ ■ ■ ■ f High-performance, EEPROM-based programmable logic devices PLDs based on second-generation Multiple Array MatriX (MAX®)

280-pin

Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family May 1999» ver. 6 Features Data Sheet ^ $ $8 M ffl M $8 j&j &£ 88 ^ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX (MAX®) architecture

Contextual Info: Configuration Elements & Reliability June 1996, ver. 3 Data Sheet Introduction Altera’s broad range of programmable logic devices PLDs incorporates four types of configuration elements: EPROM, EEPROM, FLASH, and SRAM. To ensure the highest level of device performance and reliability,

44R35

Abstract: MIFARE coil design INLAY MODULE ANTENNA CARDS
Contextual Info: ICs for Chip Cards SLE 44R35/Mifare Intelligent 1-Kbyte EEPROM with Interface for Contactless Transmission, Security Logic and Anticollision according to the MIFARE®-System Preliminary Short Product Information 07.97, Version 2.0 6/ 50LIDUH 6KRUW 3URGXFW ,QIRUPDWLRQ

TUSB2140B

Contextual Info: TUSB2077A 7ĆPORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE SLLS414 − MARCH 2000 D Universal Serial Bus USB Version 1.1 D D D D Push-Pull Outputs for PWRON Eliminate Compliant Integrated USB Transceivers 3.3-V Low Power ASIC Logic

Contextual Info: SGS-THOMSON m ST1305 HIGH ENDURANCE CMOS 192 bit EEPROM WITH SECURE LOGIC ACCESS CONTROL BRIEF DATA SINGLE 5V SUPPLY VOLTAGE PROGRAMMING TIME: 5 ms MEMORY DIVIDED INTO: Figure 1 Delivery forms - 16 bits of Chip Data - 48 bits of Application Data - 48 bits of Count Data

TUSB2140B

Contextual Info: TUSB2077A 7-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE SLLS414 – MARCH 2000 D D D D D Universal Serial Bus USB Version 1.1 Compliant Integrated USB Transceivers 3.3-V Low Power ASIC Logic Two Power Source Modes – D D

TUSB2140B

Contextual Info: TUSB2077A 7-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE SLLS414 – MARCH 2000 D D D D D Universal Serial Bus USB Version 1.1 Compliant Integrated USB Transceivers 3.3-V Low Power ASIC Logic Two Power Source Modes – D D

TUSB2140B

Abstract: m93c46 HC49U TPS2041 TPS2044 TUSB2046 TUSB2077A
Contextual Info: TUSB2077A 7-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE SLLS414 – MARCH 2000 D D D D D Universal Serial Bus USB Version 1.1 Compliant Integrated USB Transceivers 3.3-V Low Power ASIC Logic Two Power Source Modes – D D

bd05

Contextual Info: ST1305 HIGH ENDURANCE CMOS 192 bit EEPROM WITH SECURE LOGIC ACCESS CONTROL BRIEF DATA • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SINGLE 5V SUPPLY VOLTAGE PROGRAMMING TIME: 5 ms MEMORY DIVIDED INTO: – 16 bits of Chip Data – 48 bits of Application Data

NM25C04

Abstract: NM93C86A serial eeprom logic 1997
Contextual Info: Fairchild Application Note 860 Paul Bryant March 1997 TABLE OF CONTENTS 1.0 INTRODUCTION which may initiate a false write or erase cycle. This data corruption is a concern for the designer since the non-volatile nature of the EEPROM means that after data corruption has

93C46

Abstract: AN-716 AN-871 LP2953 NM93C46 93C46 national AN-871 national
Contextual Info: Fairchild Application Note 1008 Robert Stodieck March 1997 EEPROMs are useful because they are non-volatile memories that can be updated easily and quickly in a system without being physically removed. System designers working with early EEPROMs quickly learned that in addition to remembering data that they were asked to record, EEPROMs