EDI82136C20JB Search Results
EDI82136C20JB Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
QLCC 24Contextual Info: EDI82136C ^ED I B a d r o n i c D n l g n t Inc. 1 High Performance Megabit SRAM 32Kx36 Monolithic Asynchronous/Latched Address Monolithic Static RAM M M F T O f lM T M Features The EDl82136Cisa1,179,648bitAsynchronousmemoty core with transparent address and enable latches in fie |
OCR Scan |
EDI82136C 32Kx36 EDl82136Cisa1 648bitAsynchronousmemoty EDI82136C, daparitydeselectcontrolforx32bitoperation BydrecSysuppor1ingx32design 32Kx18 QLCC 24 | |
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Contextual Info: ^EDI Electronic Designs tr>c. ' , transparent latches, dual polarity single enable, master write control, master output enable, four individual byte selects x8 orx9, andaparitydeselectcontrolforx32bitoperation. This feature provides flexible control over the device array during |
OCR Scan |
daparitydeselectcontrolforx32bitoperation A0-A14 32Kx18 DQ16-DQ31 EDI82136C EDI82136C20JB EDI82136C25JB EDI82136C30JB EDI82136C35JB |