ECL10KH Search Results

K1149

Abstract: 50-to-75 RASCO k1519 ECL10KH K1149BA K1149CA K1523BA K1524AA power supply 5v dc
Contextual Info: K1149 Series ECL Compatible Oscillators ECL10KH Based Design - provides im­ proved rise and fall times, duty cycle, noise margins and power supply rejection over the earlier 10K family while retaining compatibil­ ity. Open emitter output allows the user to

Contextual Info: ECL10KH for High Performance System Design The designer of high-perform ancedigital system s now has new alternatives with the introduction o f M onolithic M em ories’ E C L 10KH fam ily of Logic. M onolithic Mem ories’ E C L 10KH devices are com pletely equivalent to M otorola’s M E C L 10KH. This

Contextual Info: ECL10KH High-Speed Emitter-Coupled Logic Family MC10H101 Quad OR/NOR Gate Features/ Benefits Ordering Inform ation • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H101 • Noise margin 150 mV PACKAGE TEMPERATURE { J,N,NL 20

MC10H101

Abstract: ECL10KH
Contextual Info: ECL10KH High-Speed Em itter-Coupled Logic Fam ily M C10H101 Quad O R/NO R Gate Ordering Inform ation Features/B enefits • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H101 PACKAGE TEMPERATURE J,N,NL 20 Com • Noise margin 150 mV

Contextual Info: ECL10KH * V l ' n Hiah-Soeed • »» »■ ■ » I 1« « Em itter-Coupled Logic Fam ily 1 1 /^ 4 A lw i\# ■ U 4 - I PRELIMINARY | in f o r m a t io n A 4 This docum ent contains spe! cifications and inform ation ■ Quad OR/NOR Gate

quad 3 input or gate

Abstract: ECL10KH MC10H131
Contextual Info: Table of Contents ECL10KH Contents for Section 13 . 13-2 Selection Guide for ECL10KH . 13-2 ECL10KH for High Performance System Design . 13-3 MC10H101 Quad OR/NOR Gate . 13-4

Contextual Info: TIEPAL10H16ET6C ECL-TO-TTLIMPACT-X PAL TRANSLATOR CIRCUIT D3283, OCTOBER 1989 JT P A C K A G E • ECL10KH Programmable Logic with ECL-to-TTL Translation ECL Control Inputs

Contextual Info: Digitally Programmable Dclsy Units SER|ES:PDU-1064H * 6-Bit E C L Interfaced Features: • ■ ■ ■ ■ ■ Low propagation delay Input & output ECL buffered 6-B IT ECL program m able delay line Output sam e polarity of input Com pletely interfaced C om pact & low profile

Contextual Info: 2-Phase Gated-Delay Line Oscillator SERIES: 16 pins DIP ECL Interfaced DLO-50 data delay p devices; m e . Features: • Continuous or keyable wavetrain. ■ Locked synchronization achieved with random gating signal. ■ Low profile module. ■ Available from 50 MHZ to 100 MHZ

H158

Abstract: ECL10KH MC10H158 FW00
Contextual Info: ECL 10KH High-Speed Emitter-Coupled Logic Family MC10H158 QUAD 2-Input Multiplexer p r e l im in a r y ' in f o r m a t io n T h is d o c u m e n t contains, spec ific a tio n s and in fo rm a tio n | w h ic h are subject, to cha n g e . I Ordering Information

memorias

Abstract: ECL10KH MC10H106
Contextual Info: EC L10K H High Speed Em itter Coupled Logic Fam ily M C 10H 106 IH p le 4 -3 -3 Input NOR Gate Features/ Benefits Ordering Inform ation • Propagation delay, 1 ns typical PART NUMBER PACKAGE MC10H106 J, N, NL TEMPERATURE • 36 mW typical/gate no load • Noise margin 150 mV

ECL10KH

Abstract: MC10H130 MC10H131
Contextual Info: ECL 10KH High-Speed Em itter-Coupled Logic Fam ily Dual Latch M C 10H 130 F eatures/ Benefits O rdering Inform ation • Propagation delay, 1 ns typical PART NUMBER PACKAGE TEMPERATURE MC10H130 J,N,NL 20 Com • Power dissipation, 155 mW typical • Noise margin 150 mV

ECL10KH

Abstract: MC10H161
Contextual Info: ECL 10KH High-Speed Em itter-Coupled Logic Fam ily M C10H161 Binary to 1 -of-8 Decoder O rdering Inform ation Features/ Benefits • Propagation delay, 1 ns typical PART NUMBER PACKAGE TEMPERATURE MC10H161 J,N,NL 20 Com • Power dissipation, 315mW typical

ecl10kh

Abstract: MC10H209
Contextual Info: E C L 1 0 K H High Speed Em itter Coupled Logic Fam ily M C 10H 209 Dual 4-5 Input OR/NOR Gate Features/Benefits • Propagation delay, 0.75 ns typical Ordering Information PART NUMBER PACKAGE TEMPERATURE M C10H209 J,N ,IMI- Com • 125 mW typical no load

micro servo 9g

Abstract: uPa2003 micro servo 9g tower pro 2SK1060 uPD3599 201 Zener diode 2SK2396 upc1237 infrared sensor TSOP - 1836 2SK518
Contextual Info: The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call

PWC-11-10

Abstract: PWC-11-15 PWC-11-20 PWC-11-25 PWC-11-6 PWC-11-7 PWC-11-8 PWC-11-9
Contextual Info: Pulse Width Controller SERIES: ECL Interfaced 16 pins DIP PWC-11 data VM/ delay ^O/ devicesYinc. Features: • ■ ■ ■ ■ Exact control of pulse width Rising edge trigger Auto-insertable ECL input & outputs High speed * r '$ E , Specifications: ■ ■

ECL10KH

Abstract: MC10H103
Contextual Info: ECL 1 0K H H igh-Speed E m itter-C oupled Logic Fam ily M C 10H 103 Quad 2 -In p u t OR G ate O rd e rin g Inform ation F e a tu re s / B e n e fits • Propagation delay, 1.0 ns typical PART NUMBER • Power dissipation 25 mW/gate MC10H103 • Noise margin 150 mV

C10H210

Contextual Info: D T j b 3 D3 4 1 0 O O O b l ö i MONOLITHIC MEMORIES IN C fll E C L 10 KH High-Speed Emitter-Coupled Logic Fam ily M C 10H 210/M C 10H 211 3-Input, 3-Output O R /N O R Gates Features/Benefits °r T -4 3 -2 1 Ordering Information • Propagation delay, 1.0 ns typical

quad 4 to 1 mux

Contextual Info: ECL 10KH High-Speed Emitter-Coupled Logic Family M C 10H 174 D ual4-to-1 M ultiplexer Features/ Benefits Ordering Information • Propagation delay 1.5 ns typical I PART NUMBER PACKAGE TEMPERATURE j J,N,NL 20 Com • Power dissipation, 305 mW typical • Noise margin 150 mV

max2923

Abstract: ecl 10K
Contextual Info: ECL 10KH High-Speed Emitter-Coupled Logic Family MC1 OH 102/Q uad 2-Input NOR Gate M C 10H 105/Triple 2 -3 -2 Input OR/NOR Gate Ordering Inform ation Features/B enefits • Propagation delay, 1 ns typical PART NUMBER • Power dissipation 25 mW/gate PACKAGE

C10H159

Contextual Info: I PRELIMINARY INFORMATION E C L 10KH High-Speed Emitter-Coupled Logic Family M C10H159 Quad 2-Input Inverting Multiplexer with Enable This docum ent contains spe­ cifications and inform ation which are subject to change. Features/Benefits Ordering Information

d3177

Contextual Info: EC L 10KH High-Speed Emitter-Coupled Logic Family M C 10H 173 QUAD 2-Input Multiplexer With Latch Features/Benefits PRELIMINARY INFORMATION T h is d o c u m e n t c o n ta in s s p e ­ c ific a tio n s a n d in fo rm a tio n w h ic h a re s u b je c t to c h a n g e .

Contextual Info: data W3V/ delay W devices/inc. Digital Delay Units SERIES DDU-12H 10 Taps ECL Interfaced Test Conditions: inp u t p u ls e -w id th : 1 5 0 % o f to tal d elay. In p u t pulse rise -tim e: « 6 ns. In p u t p ulse vo ltag e: ,7V Features: • Input & Output ECL Buffered

Contextual Info: Digitally Programmable Delay Units S ER IES : PDU-10256H 8-Bit E C L Interfaced Test Conditions Specifications: • In p u t p u ls e -w id th : ■ Delay variation: Monotonic in one direction. ■ Programmed delay tolerance: ± 5% or 2 ns whichever is greater.