EIA-644
Abstract: PECL-to-SN64LVDS33
Text: Interface Data Transmission Texas Instruments Incorporated The SN65LVDS33/34 as an ECL-to-LVTTL converter By Chris Sterzik Applications Specialist, Interface Products Introduction Figure 1. ECL characteristic load Emitter-coupled logic (ECL) has often been the physical
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SN65LVDS33/34
SLYT132
EIA-644
PECL-to-SN64LVDS33
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Untitled
Abstract: No abstract text available
Text: DP8480A DP8480A 10k ECL to TTL Level Translator with Latch Literature Number: SNOSBN8A DP8480A 10k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs
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DP8480A
DP8480A
16-pin
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Untitled
Abstract: No abstract text available
Text: DP8482A DP8482A 100k ECL to TTL Level Translator with Latch Literature Number: SNOSBO0A DP8482A 100k ECL to TTL Level Translator with Latch General Description Features This circuit translates ECL input levels to TTL output levels and provides a fall-through latch The TRI-STATE outputs
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DP8482A
DP8482A
16-pin
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Untitled
Abstract: No abstract text available
Text: 100329 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register Literature Number: SNOS122A 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels
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SNOS122A
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Abstract: No abstract text available
Text: 100324 100324 Low Power Hex TTL-to-ECL Translator Literature Number: SNOS128A 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible
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SNOS128A
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F100K ECL 300 series and design guide
Abstract: F100K ECL book F100K AN-780
Text: Fairchild Semiconductor Application Note May 1991 Revised February 2004 Operating ECL from a Single Positive Supply Introduction ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the
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AN-780
F100K ECL 300 series and design guide
F100K ECL book
F100K
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DP8481
Abstract: No abstract text available
Text: DP8481 DP8481 TTL to 10k ECL Level Translator with Latch Literature Number: SNOSBN9A DP8481 TTL to 10k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with
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DP8481
DP8481
16-pin
C199/clocks
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Untitled
Abstract: No abstract text available
Text: DP8483 DP8483 TTL to 100k ECL Level Translator with Latch Literature Number: SNOSBO1A DP8483 TTL to 100k ECL Level Translator with Latch General Description Features This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with
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DP8483
DP8483
16-pin
C1995
586/clocks
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F100K ECL 300 series and design guide
Abstract: ESD diode ,F100K ECL book AN-780 F100K F100K ECL book
Text: Fairchild Semiconductor Application Note May 1991 Revised May 2000 Operating ECL from a Single Positive Supply INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the
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F100K ECL 300 series and design guide
Abstract: F100K ECL book AN-780 F100K300 ,F100K ECL book F100K F100K ECL 300 series databook and design guide
Text: Fairchild Semiconductor Application Note 780 May 1991 INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply. This is the optimum operating configuration for ECL but not the only one. Operating ECL from a positive VCC supply is a practical
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B199 RF transistor datasheet
Abstract: F100K ECL 300 series and design guide AN-780 C1995 F100K 7474-ttl AN-780 national F100K ECL book
Text: National Semiconductor Application Note 780 John Davis May 1991 INTRODUCTION ECL is normally specified for operation with a negative VEE power source and a negative VTT termination supply This is the optimum operating configuration for ECL but not the only one Operating ECL from a positive VCC supply is a
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uA 741 IC pin configuration
Abstract: internal circuit diagram of IC 741 ic 741 datasheet internal diagram of 741 IC uA 741 OF IC 741 pin diagram of ic 741 uA 741 IC shift register ic pdf of 741 ic
Text: VITESSE SEMICONDUCTOR CORPORATION Preliminary Datasheet 500 Mb/s Video Shift Register IC VSC6424 Features • ECL and TTL I/Os: ECL for high-speed interface, TTL for low-speed interface • Multiplex or Demultiplex Operation • Selectable Shift Register Length
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VSC6424
500Mb/s
250Mb/s
Bt424
VSC6424
40-bit
G52236-0,
uA 741 IC pin configuration
internal circuit diagram of IC 741
ic 741 datasheet
internal diagram of 741 IC
uA 741
OF IC 741
pin diagram of ic 741
uA 741 IC
shift register ic
pdf of 741 ic
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Untitled
Abstract: No abstract text available
Text: ECL OSCILLATORS OEN/OEP SERIES 14 PIN ECL CLOCK OSCILLATORS APPLICATIONS: VIDEO, HIGH SPEED LOGIC Typical Electrical Characteristics Frequency Range : 30.0 MHz to 250.0 MHz Supply Voltage : OEN = -5.2V OEP = 5.0V Output Symmetry : 40% Min- 60% Max Rise Time TR
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ICD2062A
Abstract: ICD2062B
Text: ICD2062B Dual Programmable ECL/TTL Clock Generator to produce the following: a 10 K compatible complementary ECL output signal for highĆspeed video RAMDACs, a highĆspeed TTL output signal for video RAMs and system logic operation, and the requisite load, control, and clock
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ICD2062B
165MHz
ICD2062B
ICD2062A
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Untitled
Abstract: No abstract text available
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SN65EL16
SLLS921
250-ps
MC10EL16,
MC100EL16
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T0404
Abstract: No abstract text available
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SN65EL16
SLLS921
250-ps
MC10EL16,
MC100EL16
T0404
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SN65LVDS108
Abstract: SN65LVDS116
Text: Interface Data Transmission Texas Instruments Incorporated Power consumption of LVPECL and LVDS By Chris Sterzik Applications Specialist, Interface Products Introduction Figure 1. Models of ECL and LVDS output drivers and terminations Single-ended emitter-coupled logic (ECL) has
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SLYT127
SN65LVDS108
SN65LVDS116
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T0404
Abstract: T0402 capacitor MC100EL16 MC10EL16 SN65EL11 SN65EL16 SN65EL16D SN65EL16DGK
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SN65EL16
SLLS921
250-ps
MC10EL16,
MC100EL16
T0404
T0402 capacitor
MC100EL16
MC10EL16
SN65EL11
SN65EL16
SN65EL16D
SN65EL16DGK
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Untitled
Abstract: No abstract text available
Text: SN65EL16 www.ti.com. SLLS921 – NOVEMBER 2008 5-V ECL Differential Receiver
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SN65EL16
SLLS921
250-ps
MC10EL16,
MC100EL16
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Untitled
Abstract: No abstract text available
Text: SN65LVEL11 www.ti.com. SLLS927 – DECEMBER 2008 3.3 V ECL 1:2 Fanout Buffer
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SN65LVEL11
SLLS927
MC10LVEL11,
MC100LVEL11
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Q20P010
Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Text: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability
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Q20000
Q20000
0Q03RL
Q20P010
Q20M100
carry look ahead adder
Q20080
Q20P025
Q20025
vernier
Q20004
Q20010
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MPD1750-04
Abstract: SC9103-07 ttl ecl
Text: Monolithic Multi-Throw Driver Chips 03Alpha MPD1750-04 Features • 4 ns Video Switching Time ■ Low in Band Noise: -5 0 dBm at 1 GHz ■ True Differential Inputs ■ Compatible with TTL, ECL, and CMOS to 5.0V ■ Internal Referenced for TTL, ECL ■ Inverting, Non-Inverting
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MPD1750-04
03Alpha
MPD1750-04
SC9103-07
ttl ecl
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lm385 IC circuit diagram
Abstract: MC10324 eia 343 LM385/MAX4135/MAX4136/MAX4137/LM385/MAX4135/MAX4136/MAX4137/2n7000 equivalent
Text: MOTOROLA SEMICONDUCTOR MC10324 TECHNICAL DATA Advance Information 8-Bit Video DAC with ECL Inputs 8-BIT VIDEO DAC with ECL INPUTS The MC10324 is a 40 MegaSample Per Second MSPS 8-bit Video DAC capable of directly driving a 75 S2 cable, with appropriate terminations, to EIA-170 and EIA-343-A video levels. The logic inputs
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MC10324
MC10324
EIA-170
EIA-343-A
HB205)
lm385 IC circuit diagram
eia 343
LM385/MAX4135/MAX4136/MAX4137/LM385/MAX4135/MAX4136/MAX4137/2n7000 equivalent
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Untitled
Abstract: No abstract text available
Text: Telecommunications Products Product Summary Product Family Description . - :• Featuret ■ . .■ . . Serial Data up to 2.5 Gb/s ECL 1OOK Compatible Parallel Data I/O Single ECL Power Supply: VEE = -5.2 V 1.5 W Pcwer Dissipation Typ. 28-pin Ceramic LDCC Package
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STS-48
VS8004/8005
28-pin
344-pin
VSC8111EV
VSC8112
VSC864A-2
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