ECL IC BUFFER Search Results

signal path designer

Contextual Info: PRELIMINARY D E V IC E S P E C IF IC A T IO N 320000 SERIES ECL/TTL "TURBO" LOGIC ARRAYS 020000 FEATURES PERFORMANCE SUMMARY PARAMETER Typical gate delay* Maximum toggle frequency Maximum TTL input frequency Maximum TTL output frequency Maximum ECL input frequency

10K series ECL

Abstract: 014H
Contextual Info: MBM10415AH F U J IT S U M IC R O E L E C T R O N IC S. IN C . ECL 1024-BIT BIPOLAR RANDOM ACCESS MEMORY DESCRIPTION The Fujitsu MBM10415AH is a ful­ ly decoded 1024-bit ECL read/ write random access memory designed for high-speed scratch pad, control and buffer storage

MB7072E

Contextual Info: FU JITSU MB7072E M IC R O E L E C T R O N IC S . INC. ECL 256 X 4-BIT BIPOLAR RANDOM ACCESS MEMORY DESCRIPTION The Fujitsu MB7072 is a fully decoded 1024-bit ECL read/write random access memory designed for high-speed scratch pad, con­ trol and buffer storage applica­

Contextual Info: MOTOROLA SEMICONDUCTOR bftE D •_L3b72S2 □D'ìSDfiH TÛT IM0T4 MO TO RO LA SC L O G IC 1 TECHNICAL DATA Product Preview Dual Differential ECL to TTL Translator MC10ELT25 MC100ELT25 The MC10ELT/100ELT25 is a differential ECL to TTL translator Because ECL levels are used a +5V, -5.2V (or -4.5V) and ground are

Q20P010

Abstract: Q20M100 carry look ahead adder Q20080 Q20P025 Q20025 vernier Q20000 Q20004 Q20010
Contextual Info: D EV IC E SP EC IFIC A TIO N LOGIC ARRAYS Q20000 “TURBO” ECL/TTL Q20000 FEATURES Figure 6. Q20080 Die • • • • • • • • • • Up to 18,777 gates, channelless architecture 100 ps equivalent gate delays Low power 0.5-1.0 mW/gate 10K, 10KH, 10OK ECL and mixed ECL/TTL capability

Contextual Info: s e m ic o n d u c t o r Revised November 1999 100398 Quad Differential ECL/TTL Translating Transceiver with Latch General Description Features The 100398 is a quad latched transceiver designed to con­ vert TTL logic levels to differential F100K ECL logic levels

Contextual Info: s e m ic o n d u c t o r Revised November 1999 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description Features The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic lev­

Contextual Info: FUJITSU MIC ROE LE CT RON IC S F U J IT S U 23E D • 374T7L2 OÛOfla'ïS 5 BIPOtAR- RANDOIVP ACCESS MEMORY» MBM100480A-10 May 1988 Edition 1.0 16384-BIT BIPOLAR ECL RANDOM ACCESS MEMORY The Fujitsu MBM100480A It a fully decoded 16384-blt ECL read/write random access

Contextual Info: I R C H January 1992 iL D s e m ic o n d u c t o r Revised November 1999 100397 Quad Differential ECL/TTL Translating Transceiver with Latch General Description Features The 100397 is a quad latched transceiver designed to con­ vert TTL logic levels to differential F100K ECL logic levels

Contextual Info: s e m ic o n d u c t o r 100329 Low Power Octal ECL/TTL Bidirectional Translator with Register General Description Features The 100329 is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic lev­ els and vice versa. The direction of the translation is deter­

Fairchild 100K series ECL

Contextual Info: R C H II- D • M IC O N D U C T O R r 100329A Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329A is an octal registered bidirectional translator designed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determined

Contextual Info: S E M IC O N D U C T O R tm 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description Features The 100328 is an octal latched bi-directional translator de­ signed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is determined

Contextual Info: I R C H I L D S E M IC O N D U C T O R tm Low Power Octal ECL/TTL Bidirectional Translator with Register General Description The 100329A is an octal registered bidirectional translator designed to convert T T L logic levels to 100K ECL logic levels and vice versa. The direction of the translation is determ ined

F100K

Abstract: S010971 TN 10-35 diode
Contextual Info: S E M IC O N D U C T O R tm 100397 Quad Differential ECL/TTL Translating Transceiver with Latch General Description The 100397 is a quad latched tran sce ive r designed to con­ vert T T L logic levels to differential F100K ECL logic levels and vice versa. This device w as designed with th e capability

Contextual Info: CXB1505Q-Y SONY. Triple Fan-Out Buffer with Common Enable and Differential Output_ Description The CXB1505Q-Y is an ultra high speed monolithic ECL IC, which contains three Line Drivers. Each driver has two paires of differential output pins QnA,

Contextual Info: S E M IC O N D U C T O R tm 100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description Features The 100328 is an octal latched bi-directional tra n sla tor de­ signed to convert T T L logic levels to 100K ECL logic levels and vice versa. The direction o f this translation is determ ined

Contextual Info: 100128 E g l N a tio n a l Æ A S e m ic o n d u c to r F100128 ECL/TTL Bi-Directional Translator General Description The F100128 is an octal latched bi-directional translator de­ signed to convert TTL logic levels to 100K ECL logic levels and vice versa. The direction of this translation is deter­

t04 68 3 pin diode

Abstract: "Frequency Synthesizers" RAMDAC DIP vga LHi 978 ICD2062A ICD2062B ICD2062-BSC-2 3S03 Bt457
Contextual Info: IC designs Graphics Frequency Synthesizers ICD2062B Dual Programmable ECL/TTL Clock Generator Single-Chip Dual Programmable Oscillator Handles All Frequency Requirements of High-Performance Graphic Systems 2nd Generation Dual Oscilla­ tor Graphics Clock Generator

Contextual Info: CXB1105Q SONY. Triple Fan-Out Buffer with Common Enable and Differential Output Description Pin Assignm ent The CXB1105Q is an ultra high speed monolithic ECL IC, which contains three Line Drivers. Each driver has two pa ires of differential output pins QnA,

Contextual Info: IC designs Graphics Frequency Synthesizers ICD2062B Dual Programmable ECL/TTL Clock Generator Single-Chip Dual Programmable Oscillator Handles All Frequency Requirements of High-Performance Graphic Systems • 2nd Generation Dual Oscilla­ tor Graphics Clock Generator

bt ramdac

Abstract: 2062T YP167
Contextual Info: IC d esig n s Graphics Frequency Synthesizers ICD2062B Dual Programmable ECL/TTL Clock Generator Single-Chip Dual Programmable Oscillator Handles All Frequency Requirements of High-Performance Graphic Systems 2nd Generation Dual Oscilla­ tor Graphics Clock Generator

VCLK generator ttl

Abstract: icd2062a RAMDAC DIP vga
Contextual Info: IC d esig n s Graphics Frequency Synthesizers ICD2062B Dual Programmable ECL/TTL Clock Generator Single-Chip Dual Programmable Oscillator Handles All Frequency Requirements of High-Performance Graphic Systems 2nd Generation Dual Oscilla­ tor Graphics Clock Generator

AD345KY

Abstract: AD394 AD96687
Contextual Info: ANALOG D EV IC ES □ FEATURES 100MHz Driver Operation Driver Inhibit Tristate Function Guaranteed Industry Specifications 50ft Output Impedance IW ns Slew Rate Variable Output Voltages for ECL, TTL and CMOS High-Speed Differential Inputs for Maximum Flexibility

AD345KY

Abstract: AD394 AD96687 AD345
Contextual Info: ANALOG D EV IC ES □ FEATURES 100MHz Driver Operation Driver Inhibit Tristate Function Guaranteed Industry Specifications 50ft Output Impedance IW ns Slew Rate Variable Output Voltages for ECL, TTL and CMOS High-Speed Differential Inputs for Maximum Flexibility