9434
Abstract: CY101E383 EME-6300H
Text: Reliability Report QTP# 94346/95255, Version 1.0 June, 1996 BiCMOS ECL-TTL/TTL-ECL TRANSLATOR MARKETING PART NUMBERS DESCRIPTION CY101E383 ECL/TTL/ECL Translator and High Speed Bus Driver CY10E383 ECL/TTL/ECL Translator and High Speed Bus Driver CYPRESS SEMICONDUCTOR
|
Original
|
PDF
|
CY101E383
CY10E383
CY101E383-JC
9434
CY101E383
EME-6300H
|
CY101E383
Abstract: E383 R2170 ecl 84
Text: E383 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tPD TTL-to-ECL Functional Description The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-perfor-
|
Original
|
PDF
|
CY101E383
CY101E383
8-A-00023
E383
R2170
ecl 84
|
SG86A
Abstract: SG53A sg72a LVEP17 MC100ELxxx EP809 LVEL40 SLVS TR30 AND8020
Text: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than
|
Original
|
PDF
|
AN1568/D
SG86A
SG53A
sg72a
LVEP17
MC100ELxxx
EP809
LVEL40
SLVS
TR30
AND8020
|
CAN split termination
Abstract: SG86A SG53A AN1568
Text: AN1568/D Interfacing Between LVDS and ECL Prepared by: Paul Lee Logic Applications Engineer ON Semiconductor http://onsemi.com APPLICATION NOTE ECL levels Today’s applications typically use ECL devices in the PECL mode. PECL Positive ECL is nothing more than
|
Original
|
PDF
|
AN1568/D
r14525
AN1568/D
CAN split termination
SG86A
SG53A
AN1568
|
ecl 10K
Abstract: RCD Components E1001 E1004 E1008 E103 E105 SCHEMAT
Text: PRELIMINARY ECL DIGITAL DELAY LINES - 5-41-5 - ECL 10K INTERFACED - 5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay nS 3 20 4 25 5 30 6 2X Total Delay Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate
|
Original
|
PDF
|
|
XEP56V
Abstract: SY100EP56VK4GTR MC100EP56DT MC100EP56DTR2 SY100EP56V SY100EP56VK4G SY100EP56VK4I SY100EP56VK4ITR
Text: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle
|
Original
|
PDF
|
SY100EP56V
100ps
230ps
500ps
20-pin
SY100EP56V
M9999-120505
XEP56V
SY100EP56VK4GTR
MC100EP56DT
MC100EP56DTR2
SY100EP56VK4G
SY100EP56VK4I
SY100EP56VK4ITR
|
XEP56V
Abstract: No abstract text available
Text: ECL Pro 3.3V/5V PECL/ECL 3GHz DUAL DIFFERENTIAL 2:1 MULTIPLEXER Micrel, Inc. SY100EP56V ECL Pro™ SY100EP56V FEATURES • Dual, fully differential 2:1 PECL/ECL multiplexer ■ Guaranteed AC parameters over temperature/ voltage: • > 3GHz fMAX toggle
|
Original
|
PDF
|
SY100EP56V
SY100EP56V
100ps
230ps
500ps
20-pin
M9999-070105
XEP56V
|
marking Ed11
Abstract: No abstract text available
Text: PECL, ECL, LVDS Page 1 - 6 Pl tronics,. Inc. 19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA Manufacturer of High Quality Frequency Control Products ED1145M ECL Series Full Size Metal Thru-Hole ECL Oscillator Differential or NonDifferential ECL Output without Enable/Disable
|
Original
|
PDF
|
ED1145M
EC1145M:
EC1144M:
EC1120M:
marking Ed11
|
XEP57V
Abstract: marking k4 XEP57
Text: ECL Pro 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel ECL Pro™ SY100EP57V SY100EP57V FINAL FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time
|
Original
|
PDF
|
SY100EP57V
220ps
520ps
20-pin
SY100EP57V
MC10/100EP57DT.
XEP57V
marking k4
XEP57
|
MC10EP58D
Abstract: MC10EP58DR2 SY100EP58V SY10EP58V SY10EP58VZI SY10EP58VZITR
Text: ECL Pro SY10EP58V ECL Pro™ SY100EP58V 3.3V/5V 3GHz PECL/ECL 2:1 MULTIPLEXER Micrel, Inc. SY10EP58V SY100EP58V FEATURES • 2:1 PECL/ECL multiplexer ■ Guaranteed AC–performance over temperature/voltage • >3GHz fMAX toggle • <200ps rise/fall time
|
Original
|
PDF
|
SY10EP58V
SY100EP58V
200ps
420ps
15pspp
SY10/100EP58V
MC10/100EP58D/DT
M9999-070105
MC10EP58D
MC10EP58DR2
SY100EP58V
SY10EP58V
SY10EP58VZI
SY10EP58VZITR
|
XEP57V
Abstract: No abstract text available
Text: 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel, Inc. ECL Pro SY100EP57V ECL Pro™ SY100EP57V FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time
|
Original
|
PDF
|
SY100EP57V
SY100EP57V
220ps
520ps
20-pin
MC10/100EP57DT.
M9999-070105
XEP57V
|
SY100EP57VK4G
Abstract: MC100EP57DT MC100EP57DTR2 SY100EP57V SY100EP57VK4I SY100EP57VK4ITR
Text: 3.3V/5V PECL/ECL 3GHz DIFFERENTIAL 4:1 MULTIPLEXER Micrel, Inc. ECL Pro SY100EP57V ECL Pro™ SY100EP57V FEATURES • Fully differential 4:1 PECL/ECL multiplexer ■ Guaranteed AC-parameters over temp/voltage: • > 3GHz Fmax toggle • < 220ps rise/fall Time
|
Original
|
PDF
|
SY100EP57V
220ps
520ps
20-pin
SY100EP57V
MC10/100EP57DT.
M9999-120505
SY100EP57VK4G
MC100EP57DT
MC100EP57DTR2
SY100EP57VK4I
SY100EP57VK4ITR
|
Untitled
Abstract: No abstract text available
Text: SPST ECL Switches With Drivers 2662 Series V2.00 Features ● ● ● Broadband Frequency Ranges Environmentally Sealed ECL Compatible Description M/A-COM’s Emitter Coupled Logic ECL PIN diode switches offer multi-octave bands from UHF to Ku-band. Advantages of an ECL switch are narrow pulse width
|
Original
|
PDF
|
|
10H645
Abstract: E211 MC10E111 MPC973 AN1405
Text: AN1405/D ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering http://onsemi.com APPLICATION NOTE This application note provides information on system design using ECL logic technologies for reducing system clock skew over
|
Original
|
PDF
|
AN1405/D
r14525
10H645
E211
MC10E111
MPC973
AN1405
|
|
|
Untitled
Abstract: No abstract text available
Text: ECL DIGITAL DELAY LINES SERIES E10 - ECL 10K INTERFACED SERIES E100 - ECL 100K INTERFACED TEST CONDITIONS @25°C • ■ ■ ■ ■ ■ Industry’s widest selection! Economical cost, prompt delivery Fast 2nSec rise time typical Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K
|
OCR Scan
|
PDF
|
ECL10K
E1004
ECL100K
100MX
400MX
|
b765
Abstract: PAL 008 PAL10016RD8 PAL1016RD8
Text: PRELIMINARY September 1986 ECL Registered and Latched Programmable Array Logic PAL Family General Description The registered and latched ECL PAL devices are the latest additions to National Semiconductor's ECL PAL family. The ECL PAL family utilizes National Semiconductor's advanced
|
OCR Scan
|
PDF
|
2-26A
AA32096
b765
PAL 008
PAL10016RD8
PAL1016RD8
|
Untitled
Abstract: No abstract text available
Text: TIEPAL10016ET6C ECL-TO-TTLIMPACT-X" PAL TRANSLATOR CIRCUIT D3352, OCTOBER 1989 • ECL 100K Programmable Logic with ECL-to-TTL Translation JT PACKAGE TOP VIEW • ECL Control Inputs vcc[ '[ l[ l[ l[ l[ '[ '[ • 3-State TTL Outputs • IMPACT-X“ Process with Reliable
|
OCR Scan
|
PDF
|
TIEPAL10016ET6C
D3352,
300-mil
|
TL 2272 R
Abstract: PAL1016RM4AJC
Text: ECL PAL10/10016RM4A r% \ ÆM National Semiconductor PAL10/10016RM4A ECL Registered Programmable Array Logic General Description The PAL10/10016RM4A is a member of the National Semi conductor ECL PAL family. The ECL PAL Series-A is char acterized by 4 ns maximum propagation delays combinato
|
OCR Scan
|
PDF
|
PAL10/10016RM4A
PAL10/10016RM4A
PAL1016RM4A/PAL10016RM4A
TL/L/9772-10
TL 2272 R
PAL1016RM4AJC
|
Untitled
Abstract: No abstract text available
Text: ECL PAL10/10016RM4A m National ÆM Semiconductor PAL10/10016RM4A ECL Registered Programmable Array Logic General Description The PAL10/10016RM4A is a member of the National Semi conductor ECL PAL family. The ECL PAL Series-A is char acterized by 4 ns maximum propagation delays combinato
|
OCR Scan
|
PDF
|
PAL10/10016RM4A
PAL10/10016RM4A
PAL10/10016RM
Diagram--PAL1016RM4A/PAL10016RM4A
|
CY101E383
Abstract: E383 E1472
Text: fax id: 5000 i , *" : :V:V:V:V:V:g:-v- : : ^ :^ ; ^3»* i ; : M m : M : i : m : CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Features • BiCMOS for optimum speed/power • High speed max. — 3.0 ns tpQ TTL-to-ECL — 4 ns tpQ ECL-to-TTL
|
OCR Scan
|
PDF
|
80-pin
84-pin
CY101E383
CY101E383
E383
E1472
|
Untitled
Abstract: No abstract text available
Text: TIEPAL10H16ET6C ECL-TO-TTLIMPACT-X PAL TRANSLATOR CIRCUIT D3283, OCTOBER 1989 JT P A C K A G E • ECL10KH Programmable Logic with ECL-to-TTL Translation ECL Control Inputs
|
OCR Scan
|
PDF
|
TIEPAL10H16ET6C
D3283,
ECL10KH
300-mil
|
Untitled
Abstract: No abstract text available
Text: ECL DIGITAL DELAY LINES RESISTORS •CAPS » COILS •DELAY U NES E10 SERIES - ECL10KINTERFACED E100 SERIES - ECL 100K INTERFACED FEATURES □ Industry’s widest selection! □ Economical cost, prompt delivery □ Fast 2nSec rise time typical □ Standard 16 pin DIP on ECL 10K, 24 pin DIP on ECL 100K
|
OCR Scan
|
PDF
|
ECL10KINTERFACED
dow00K
|
Untitled
Abstract: No abstract text available
Text: PAL10/10016P8 ECL Programmable Array Logic ECL PAL10/10016P8 National Semiconductor General Description The PAL1016PB/10016P8 is the first member of an ECL programmable logic device family possessing common electrical characteristics, utilizing an easily accommodated
|
OCR Scan
|
PDF
|
PAL10/10016P8
PAL10/10016P8
PAL1016PB/10016P8
|
Untitled
Abstract: No abstract text available
Text: AN1405 Application Note ECL Clock Distribution Techniques Prepared by Todd Pearson ECL Applications Engineering This application note provides information on system design using ECL logic technologies for reducing system clock skew over the alternative CMOS and TTL
|
OCR Scan
|
PDF
|
AN1405
BR1333
|
