Untitled
Abstract: No abstract text available
Text: SDR SDRAM E0342M21 Ver.2.1 February 2004 (K) Japan PRELIMINARY DATA SHEET M2V64S50ETP 64M Single Data Rate Synchronous DRAM DESCRIPTION M2V64S50ETP is a 4-bank x 524,288-word x 32-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK.
|
Original
|
PDF
|
E0342M21
M2V64S50ETP
M2V64S50ETP
288-word
32-bit,
100MHz
133MHz
166MHz
M01E0107
|
sdr sdram reference
Abstract: M2V64S50ETP
Text: SDR SDRAM E0342M21 Ver.2.1 February 2004 (K) Japan PRELIMINARY DATA SHEET M2V64S50ETP 64M Single Data Rate Synchronous DRAM DESCRIPTION M2V64S50ETP is a 4-bank x 524,288-word x 32-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK.
|
Original
|
PDF
|
E0342M21
M2V64S50ETP
M2V64S50ETP
288-word
32-bit,
100MHz
133MHz
166MHz
M01E0107
sdr sdram reference
|