DYNAMIC RAM CMOS 16PIN Search Results

Contextual Info: MEMORY 1M X 16 BIT FAST PAGE MOBEDYNAMICRA MB81V16160B-50/-60/-50L/-60L CMOS 1,048,576 x 16 Bit Fast Page Mode Dynamic RAM DESCRIPTION The Fujitsu MB81V16160B is a fully decoded CMOS Dynamic RAM DRAM that contains 16,777,216 memory cells accessible in 16-bit increments. The MB81V16160B features a ‘last page” mode of operation whereby

MB81C258-12

Abstract: c258 MB81C258 MB81C258-10
Contextual Info: FU JITSU 262144 BIT CMOS STATIC COLUMN DYNAMIC RAM MB81C258-10 MB81C258-12 MB81C258-15 1 1 1 O c to b e r 1 9 8 8 E d itio n 3 .0 262,144 x 1 BIT CMOS STATIC COLUMN DYNAMIC RAM The Fujitsu MB 81C258 is CMOS static colum n dynam ic random access memo­ ry, SC-DRAM, w hich is organized as 262144 w ord by 1 bit. This SC-DRAM is

Contextual Info: s -n o y 0 0 1 8 9 1 tfY i ^ j& P R E L IM IN A R Y f t SEMICONDUCTOR HY51C64 65,536X1-Bit CMOS Dynamic RAM FEBRUARY 1986 DESCRIPTION The HY51C64 is a high speed 65,536 bit CMOS dynamic Random Access Memory. Fabricated in CMOS technology, the HY51C64 offers features not

HY53C256

Abstract: HY53C256LS
Contextual Info: HYUNDAI HY53C256 Series 256Kx1-bit CMOS DRAM DESCRIPTION The HY53C256 is fast dynamic RAM organized 262,144 x 1-bit. The HY53C256 utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins to the users.

HY53C256LS

Abstract: HY53C256S-70 HY53C256 HY53C256LF HY53C256LS70
Contextual Info: HYUNDAI HY53C256 Series 256KX 1-bit CMOS DRAM DESCRIPTION The HY53C256 is fast dynamic RAM organized 262,144 x 1-bit. The HY53C256 utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins to the users.

MAY94

Abstract: vve.3 HY53C256 A08H
Contextual Info: HY53C256 Series HYUNDAI 256K x1-bit CMOS DRAM DESCRIPTION The HY53C256 is fast dynamic RAM organized 262,144 x 1-bit. The HY53C256 utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins to the users.

Contextual Info: Am90C257 256K x 1 CMOS Static Column Dynamic RAM DISTINCTIVE CHARACTERISTICS • • C ontinuous data rate over 25 MHz Lower pow er dissipation via CMOS process - 20-m W standby mode -3 0 0 -m W operating mode High-speed operation - 80-ns RAS access tim es

bc6 csr

Abstract: CSR BC6 wf vqc 10 d a6 LC32256 LC32256P
Contextual Info: Ordering number : EN4700B CMOS LSI LC32256P-80 256 K 262144 words x 1 bit DRAM Fast Page Modem Overview The LC32256P is a CMOS dynamic RAM operating on a single 5 V power source and having a 262144 words x 1 bit configuration. Equipped with high speed and low

Contextual Info: Am 90C 257 256K x 1 CMOS Static Column Dynamic RAM ADVANCE INFORMATION DISTINCTIVE CHARACTERISTICS • • Continuous data rate over 25 MHz Lower power dissipation via CMOS process - 20-mW standby mode -300-m W operating mode • • • High-speed operation - 80-ns RAS access times

HY53C256LF

Abstract: HY53C256 HY53C256LS D0022 JRC5 mb75a
Contextual Info: HY53C256 Series •HYUNDAI 256K X 1-bit CMOS DRAM DESCRIPTION f HY53C25f l fas* dynamic RAM organized 262,144 x 1-bit. The HY53C256 utilizes Hyundai’s CMOS silicon i!in|ra0C^ f SHH° 9y as WeH as advanced circuit techniques to provide wide operating margins to the users

UPD4265

Contextual Info: SEC /¿PD4265 6 5 ,5 3 6 x 1 -BIT DYNAMIC CMOS RAM NEC Electronics Inc. Revision 1 Description Pin Configuration The NEC /UPD4265 is a 65,536-word by 1-bit d ynam ic CM O S Random Access M em ory RAM designed to operate from a single + 5 V p ow er supply. The

Contextual Info: Am90C256 256K x 1 CMOS Enhanced Page Mode Dynamic RAM PRELIMINARY 9SZD06UIV DISTINCTIVE CHARACTERISTICS • • • • Continuous data rate over 25 MHz Random access within a row Flow-through column latch for pipelining Low operating current- 7 0 mA • •

AM90C255-10

Abstract: AM90C255-12 uras 14
Contextual Info: Am90C255 256K x 1 CMOS Nibble Mode Dynamic RAM PRELIMINARY SSZ006UIV DISTINCTIVE CHARACTERISTICS • • • • High density 256K x 1 Low-power dissipation — 358 mW active High-speed operation — 80-ns access, 130-ns cycle times High-speed Nibble Mode

MB81C258-12

Contextual Info: 262144 BIT CMOS STATIC COLUMN DYNAMIC RAM MB81C258-10 MB81C258-12 MB81C258-15 O ctob er 1988 E d itio n 3.0 262,144 x 1 BIT CMOS STATIC COLUMN DYNAMIC RAM T he F u jits u M B 8 1 C 2 5 8 is CM O S s ta tic c o lu m n d y n a m ic random access m e m o ­ ry , S C -D R A M , w h ic h is organized as 2 6 2 1 4 4 w o rd b y 1 b it. T his S C -D R A M is

Contextual Info: Am90C255 256K x 1 CMOS Nibble Mode Dynamic RAM Am90C255 PRELIMINARY DISTINCTIVE CHARACTERISTICS • • • • High density 256K x 1 Low-power dissipation — 358 mW active High-speed operation — 80-ns access, 130-ns cycle times High-speed Nibble Mode - 15-ns access, 35-ns cycle times

Contextual Info: Am90C255 256K x 1 CMOS Nibble Mode Dynamic RAM PRELIMINARY SSZ006WV DISTINCTIVE CHARACTERISTICS • • • High density 256K x 1 Low-power dissipation — 358 mW active High-speed operation — 80-ns access, 130-ns cycle times • High-speed Nibble Mode - 15-ns access, 35-ns cycle times

Contextual Info: VITELIC V51C64 FAMILY HIGH PERFORMANCE LOW POWER 65,536x1 BIT CMOS DYNAMIC RAM V51C64-10 V51C64L-10 V51C64-12 V51C64L-12 V51C64-15 V51C64L-15 100 160 35 100 160 35 120 190 45 120 190 45 150 245 55 150 245 55 Maximum Access Time ns Minimum Cycle Time (ns)

Contextual Info: VITELIC CORP A3 'ÌSDS310 00ODI11 □ i ~ 9502310 VITELIC CORP V IT E L IC 83P 00111 0 7 - V51C64 FAMILY HIGH PERFO RM AN CE LOW POWER 65,536x1 BIT CMOS DYNAMIC RAM V51C64-10 V51C64L-10 V51C64-12 V51C64L-12 V51C64-15 V51C64L-15 100 160 35 100 160 35 120 190

k22s

Abstract: HP 1003 WA
Contextual Info: iw VITELIC V53C258A FAMILY HIGH PERFORMANCE, LOW POWER 2 5 6 K X 1 B IT STATIC COLUMN CMOS DYNAMIC RAM ‘ 60/60L HIGH PERFORMANCE V53C25SA 70/70L 80/80L 10/10L Max. RAS Access Time, tRAC 60 ns 70 ns 80 ns 100 ns Max. Column Address Access Time, (tCAA) 30 ns

Contextual Info: IW VITELIC V53C258A FAMILY HIGH PERFORMANCE, LOW POWER 2 5 6 K X 1 B IT STATIC COLUMN CMOS DYNAMIC RAM ‘ 60/60L HIGH PERFORMANCE V53C258A tRAC 70/70L 80/80L 10/10L 60 ns 70 ns 80 ns 100 ns Max. Column Address Access Time, (tCAA) 30 ns 35 ns 40 ns 45 ns

V51C64L-15

Abstract: celica V51C64-10 V51C64-12 V51C64-15 V51C64L-10 V51C64L-12
Contextual Info: V IT E U C V51C64 FAMILY HIGH PERFORMANCE LOW POWER 6 5 ,5 3 6 x 1 B IT CMOS DYNAMIC RAM V51C64-10 V51C64L-10 V51C64-12 V51C64L-12 V51C64-15 V51C64L-15 100 160 35 100 160 35 120 190 45 120 190 45 150 245 55 150 245 55 Maximum Access Time ns Minimum Cycle Time (ns)

16PIN

Abstract: 51C64H-12 51C64H-8 51C64HL-12 51C64L-12 51C65L-10 51C65L-12 HY51C64-10 HY51C64-12 HY51C64-15
Contextual Info: - 172 — 64K A • m m m % it £ OC TRCY TCAD TAH TRAC max n s) ■ in (n s) CMOS Dynamic 4 7 f y / U f t ■ in (n s) ■in (n s) TP ■ in (n s) TWCY (n s) RAM(65536x1) m « TC'H ■in (n s) TfiWC n in (n s) VDD o r VCC (V) IDD nax (aA) À ID D STANDBY

MH89760B

Abstract: MH89790B MT8920B MT8920BE MT8920BP MT8920BS MT8976 MT8979 4A63 VDD52
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8920B ST-BUS Parallel Access Circuit Features • • • • • • • • ISSUE 7 High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP mode 1 Fast dual-port RAM access (mode 2) Access time: 120 nsec

74HC12

Abstract: ST-BUS MH89760B MH89790B MT8920B MT8920BE MT8920BP MT8920BS MT8976 MT8979
Contextual Info: ISO-CMOS ST-BUS FAMILY MT8920B ST-BUS Parallel Access Circuit  Features • • • • • • • • ISSUE 7 High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP mode 1 Fast dual-port RAM access (mode 2) Access time: 120 nsec