DYNA Search Results

UM5583

Abstract: UM55 SPKP rs 355 integrated circuits 5583H
Contextual Info: UMC UM5583 3 Sec Recording / Playback 1C Features • "BEEP" sound indicates to start recording and memory full for manual playback ■ Built-In AGC Automatic Gain Control to enlarge input dynamic range ■ Built-in low pass filter ■ Built-in microphone amplifier

TMS4116

Abstract: TMS4132
Contextual Info: MOS LSI TMS 4132 JDL 32,768-BIT DYNAMIC RANDOM-ACCESS MEMORY NOVEMBER 1979 32,768 «AX SUPPLY 1 X 1 Organization 10% Tolerance on All Supplies • All Inputs Including Clocks TTL-Compatible

A9RV

Abstract: 5s a315 A327
Contextual Info: TOSHIBA TC514900AJLL-70/80 524,288 WORD X 9 BIT DYNAMIC RAM DESCRIPTION The TC514900AJLL is the new generation dynamic RAM organized 524,288 word by 9 bit. The TC514900AJLL utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit

tms4256

Abstract: TMS4266
Contextual Info: INSTR TM4256EL9, TM4256GU9 262,144 BY 9-BIT DYNAMIC BAM MODULES 7“-ifc-23-/7 25E D SEPTEMBER 1986 — REVISED M ARCH 1968 A SIC /MEMORY 262,144 x 9 Organization TM4266EL9 . . . L SMQLE-IN-UNE PACKAGE (TOP VIEWl_ Slngla 5-V Supply (10% Tolerance)

4A04I

Abstract: tc514100a
Contextual Info: TC51441OAP/AJ/ASJ/AZ—70, TC51441OAP/AJ/ASJ/AZ-80 TC51441OAP/AJ/ASJ/AZ-10 PRELIMINARY 1,048,576 W ORD x 4 BIT DYNAMIC RAM DESCRIPTION The TC51441 OAP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4 bits. The TC514410AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

cq837

Contextual Info: 4J« *- »t TOSHIBA HYBRID D IG ITA L INTcGRATED CIRCUIT INTEGRATED CIRCUIT TO SHIBA THM 364080AS THM 364080ASG TECHNICAL DATA - 60. 70. 80, 10 - 60, 70, 80. 10 TENTATIVE DATA 4*194,304 W O R D S X 36 BIT D YN AM IC RA M MODULE DESCRIPTION The THM364080AS/ASG is a 4,194,304 words by 36 bits dynamic RA M module which assembled 36

BE423

Contextual Info: TOSHIBA TC5118325BJ/BFT-70 PRELIMINARY 524,288 WORD X 32 BIT EDO DYNAMIC RAM Description The TC5118325BJ/BFT is the Hyper Page Mode (EDO) dynamic RAM organized 524,288 words by 32 bits. The TC5118325BJ/BFT utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to pro­

TC514170BJ-80

Abstract: tc514170 TC514170BJ80
Contextual Info: TOSHIBA TC514170BJ-70/80 262,144 WORD X 16 BIT DYNAMIC RAM DESCRIPTION The TC514170BJ is the new generation dynam ic RAM organized 262,144 word by 16 bit. The TC514170BJ utilizes T oshiba’s CM OS silicon gate process technology as well as advanced circuit techniques

TM4SN64EPN10

Abstract: TM2SN64EPN-10 TM48N64EPN TM4SN64EPN-10 TMS626812
Contextual Info: TM2SN64EPN 2097152 BY 64-BIT TM4SN64EPN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES _ SYNCHRONOUS CLOCK CYCLE TIME *CK3 , {CL = 3 t ACCESS TIME CLOCK TO OUTPUT >CK2 CL = 2) *CK3 (CL = 3) *CK2 (CL = 2) • • • • • • • •

Contextual Info: TM4164EC4 65,536 BY 4-BIT DYNAMIC RAM MODULE NOVEMBER 1983 - REVISED NOVEMBER 1985 SINGLE-IN-UNE PACKAGE 6 5 ,5 3 6 X 4 Organization TOP VIEW Single 5-V Supply (10% Tolerance) 22-Pin Single-in-Line Package (SIP) Utilizes Four 64K Dynamic RAMs in Plastic

wc 2c

Contextual Info: SMJ4416 16.384-WORD BY 4-BIT DYNAMIC RAM AUGUST 1980 JO PACKAGE 1 6 ,3 8 4 x 4 O rg anizatio n TO P V IE W S ingle 5 -V S u p p ly ( ± 1 0 % T olerance) g P erfo rm a nce Ranges ACCESS T IM E • DQ1 C C2 DQ 2C Ul8 Dvss 17 3 D Q 4 3 16 4 15 "2C A S "2D Q 3

TC5117445CSJ

Contextual Info: TO SHIBA_ TC5117445CSJ-40,-50,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORD BY 4-BIT EDO HYPER PAGE DYNAMIC RAM DESCRIPTION The TC5117445CSJ is an EDO (Hyper Page) dynamic RAM organized as 4,194,304 words by 4 bits. The

44c256

Abstract: 3034C
Contextual Info: SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY _ SGMS034C - MAY 1989 - B E V ILO JUNE 1965 Organization. . . 262144 Words x 4 Bits Single 5-V Supply 10% Tolerance Processed to MIL-STD-833, Class B Performance Ranges: 3-State Unlatched Output

TC51V18160

Contextual Info: INTEGRATED TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TC51V18160 C S / CFTS - 60 TOSHIBA TECHNICAL DATA SILICON GATE CMOS TENTATIVE DATA 1,048,576 WORD x16 BIT FAST PAGE DYNAMIC RAM DESCRIPTION The TC51V1S160CJS-CFTS is the fast page dynamic R A M organized 1,048,576 words by 16 bits.

Contextual Info: TO SHIBA THMY644071EG-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 4,194,304-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY644071EG is a 4,194,304-word by 64-bit synchronous dynamic RAM module consisting of four TC59S6416FT DRAMs and an unbuffer on a printed circuit board.

TC528257

Abstract: n724
Contextual Info: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT DRAM DESCRIPTION The TC528257 is a 2M bit CM OS multiport m em ory equipped with a 262,144-w ords by 8 -bits dynam ic random access m em ory RAM port and a 512-words by 8 -bits static serial access m emory (SA M ) port. The

Contextual Info: h- .5 0 -H .2 5 0 r 1 .075 — .19 7 .0 5 5 I F □ □ □ .031 — r Î •lo .38 I HIGH DYNAMIC RANGE DOUBLE BALANCED MIXER h-— -19 MAX —- - T .3 5 1 TRAK MICROWAVE RF MIXER $ M X R /3 C F -0 2 H D SPECIFICATIONS: IF OPERATING FREQUENCY

Contextual Info: TM4EP72BPB, TM4EP72BJB, 4194304 BY 72-BIT TM4EP72CPB, TM4EP72CJB 4194304 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES _ _ • • • • Long Refresh Periods: - TM4EP72CxB: 64 ms 4096 Cycles

Contextual Info: PRELIMINARY 4,194,304 WORD x 1 BIT DYNAMIC RAM DESCRIPTION The TC514101AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514101AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating m argins, both internally and to the system user.

Contextual Info: h- .5 0 - - .2 5 0 |.0 7 5 — .19 r t 1 t 1 RF□ 0 5 5 -1 r .031 — c ri T -lo .38 T - .35 1 I IF MATERIAL El STANDARD □ SPECIAL ° BASE o COVER ° MARKING » FINISH F R -4 VECTRA LASER SOLDER TIN HIGH DYNAMIC RANGE DOUBLE BALANCED MIXER MAX

EN 1452-3

Abstract: J416
Contextual Info: SMJ4164 65.536-BIT DYNAMIC RANDOM-ACCESS MEMORY JU LY 1985 - J D PA C K A G E 6 5 ,5 3 6 x 1 Organization TO P V IEW Single 5-V Supply (± 1 0% Tolerance) w Ç AOQ A2C A1 C VddC 8 Long Refresh Period . . . 4 ms FG PA C K A G E Low Refresh Overhead Time . .

TC514265DJ

Abstract: TC514265D TC514265 SOJ40-P-400
Contextual Info: TOSHIBA TC514265DJ/DFT-50/60/70 PRELIMINARY 262,144 WORD X 16 BIT EDO HYPER PAGE DYNAMIC RAM Description TheTC514265DJ/DFT is an EDO (hyper page) dynamic RAM organized as 262,144 words by 16 bits. TheTC514265DJ/ DFT utilizes Toshiba's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide oper­

Contextual Info: TOSHIBA TC514800AJ/AZ/AFT-70/80 524,288 WORD X 8 BIT DYNAMIC RAM DESCRIPTION The TC514800AJ/AZ/AFT is the new generation dynam ic RAM organized 524,288 word by 8 bit. The TC514800A J/AZ/AFT utilizes T oshiba’s CM OS silicon gate process technology as w ell as advanced circuit

TC5117405

Contextual Info: TOSHIBA THM328025BS/BS&60/70 PRELIMINARY 8,388,608 WORDS X 32 BIT EDO DYNAMIC RAM MODULE Description The THM328025BS/BSG is a 8,388,608 words by 32 bits Hyper Page Mode (EDO) dynamic RAM module which assembled 16 pcs of TC5117405BSJ on the printed circuit board. This module is optimized for application to the systems which are