DWOT Search Results

25x16v

Contextual Info: SN54LV165, SN74LV165 PARALLEL-LOAD 8-BIT SHIFT REGISTERS SCES007B - MARCH 1996 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-n Process typical Vq l p (Output Ground Bounce) < 0.8 V at V c c . Ta = 25°C Typical V q h v (Output V q h Undershoot)

AL-2-22H-212

Abstract: ThermMate mini
Contextual Info: VI COR CONFIDENTIAL REV. THIS DOCUMENT AND THE DATA DISCLOSED HEREIN OR HEREWITH IS NOT TO BE REPRODUCED. USED. OR DISCLOSED IN WHOLE OR IN PART TO ANYONE WITHOUT PERMISSION OF VICOR CORP. DESCRIPTION DATE APPROVED RCM 8/14/98 KGD *6 MODIFY TO LOOK LIKE VENDOR'S DWG

D3807

Abstract: TIS34 54AC16640 74AC16640 K2226 K2027 TI0284-D3807
Contextual Info: 54AC16640, 74AC16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS TI0284—D3607, JULY 1990—REVISED OCTOBER 1990 Members of the Texas Instruments Wfdebus" Family 54AC16640 . . . WD PACKAGE 74AC16640 . . . DL PACKAGE TOP VIEW Packaged in Shrink Small Outline 300-mil

MT4C16270DJ-7

Contextual Info: M IC R O N Mi MT4C16270 256Kx 16 DRAM TtoiMxasr. MC. DRAM 256K x 16 DRAM EDO PAGE MODE FEATURES • Industry-standard x l6 pinouts, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5V ±10% power supply* • Low power, 3m W standby; 375m W active, typical

Contextual Info: I SN74LVC374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS296 - JANUARY 1993 - REVISED MARCH 1994 EPIC Enhanced-Performance Implanted CMOS Submicron Process DB, DW, OR PW PACKAGE (TOP VIEW) Typical Vq l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

81C1501

Abstract: mb81c1501
Contextual Info: November 1990 Editbn 2.0 FUJITSU DATA SHEET MB81C1501 1 M B IT 3 PORT CMOS DYNAMIC FIELD MEMORY 1,175,040 Bit 3 Port CMOS Dynamic Field Memory The Fujitsu MB81C1501 is a 293, 760-word x 4 bit 960 pixels x 306 lines field memory. The MB81C1501 has a 3-port set-up (serial input: 1 port, serial output: 3 ports) allowing

AL-2-22H-137

Abstract: ThermMate micro
Contextual Info: VI COR CONFIDENTIAL REV. THIS DOCUMENT AND THE DATA DISCLOSED HEREIN OR HEREWITH IS NOT TO BE REPRODUCED. USED. OR DISCLOSED IN WHOLE OR IN PART TO ANYONE WITHOUT PERMISSION OF VICOR CORP. DESCRIPTION #5 MODIFY TO LOOK LIKE VENDOR'S DWG «»6 ADDED ARTWORK

Contextual Info: SN54LVT2952, SN74LVT2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS I SCBS162E - MAY 1992 - REVISED JULY 199S I SN54LVT2952 . . . JT PACKAGE SN74LVT2952 . . . DB, DW, OR PW PACKAGE TOP VIEW • State-of-the-Art Advanced BICMOS Technology (ABT) Design for 3.3-V