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    DUAL TRISTATE XOR GATE Search Results

    DUAL TRISTATE XOR GATE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    GT30J110SRA Toshiba Electronic Devices & Storage Corporation IGBT, 1100 V, 60 A, Built-in Diodes, TO-3P(N) Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    DUAL TRISTATE XOR GATE Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    full subtractor circuit using xor and nand gates

    Abstract: full subtractor circuit using nor gates 4-bit full adder using nand gates and 3*8 decoder 2 bit magnitude comparator using 2 xor gates 4-bit bcd subtractor 8 bit bcd adder subtractor BCD adder and subtractor half adder using x-OR and NAND gate bcd subtractor full adder circuit using xor and nand gates
    Text: pASIC Macro Library HIGHLIGHTS More than 350 Architecturally Optimized Macros Includes Simple Gates and Advanced Soft Macros Includes Over 100 7400-Series TTL Building Blocks SpDE Packs as Many as 4 Macros Into a Single Logic Cell SpDE's Logic Optimize maps many simple gates into a single logic cell


    Original     		7400-Series 10-bit TTL244q TTL259 TTL261 TTL268q full subtractor circuit using xor and nand gates full subtractor circuit using nor gates 4-bit full adder using nand gates and 3*8 decoder 2 bit magnitude comparator using 2 xor gates 4-bit bcd subtractor 8 bit bcd adder subtractor BCD adder and subtractor half adder using x-OR and NAND gate bcd subtractor full adder circuit using xor and nand gates PDF

    74573

    Abstract: 74574 7486 XOR GATE 7486 full adder latch 74574 7408, 7404, 7486, 7432 7490 Decade Counter 74373 cmos dual s-r latch 2 bit magnitude comparator using 2 xor gates design a BCD counter using j-k flipflop
    Text: Semiconductor Logic Device Cross-Reference Here is a comprehensive cross-reference of TTL and CMOS chips that are readily available over the counter from such places as Maplin Electronics in the UK . Tables of both TTL and CMOS devices are provided along with tables grouping chips with the same functionality together.


    Original     		PDF

    NH82546GB

    Abstract: fw8254 FW82546
    Text: 82546GB Dual Port Gigabit Ethernet Controller Networking Silicon Datasheet Product Features • PCI/PCI-X — PCI-X Revision 1.0a support for frequencies up to 133 MHz — Multi-function PCI device — PCI Revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 MHz and


    Original     		82546GB 32-bit 64-bit 82546GB NH82546GB fw8254 FW82546 PDF

    FW82546EB

    Abstract: 82546EB 82544GC 82545EM 82545GM
    Text: 82546EB Dual Port Gigabit Ethernet Controller Networking Silicon Datasheet Revision 2.1 October 2005 Revision History Revision Date Description 2.1 Oct 2005 Changed interrupt signals INTA# and INTB# symbol types from TS tri-state to OD (open drain). 2.0


    Original     		82546EB FW82546EB 82544GC 82545EM 82545GM PDF

    Untitled

    Abstract: No abstract text available
    Text: 82546EB Dual Port Gigabit Ethernet Controller Networking Silicon Datasheet Revision 2.0 June 2005 Revision History Revision Date Description 2.0 June 2005 Added Specification Change, Specification Clarification, and Document Change information from the 82546EB Gigabit Ethernet Controller Specification Update Revision 2.0.


    Original     		82546EB 82546EB PDF

    364-pin

    Abstract: NH82546GB intel
    Text: 82546GB Dual Port Gigabit Ethernet Controller Networking Silicon Datasheet Product Features • ■ ■ PCI/PCI-X — PCI-X Revision 1.0a support for frequencies up to 133 MHz — Multi-function PCI device — PCI Revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 MHz and


    Original     		82546GB 32-bit 64-bit 82546GB 364-pin NH82546GB intel PDF

    intel 82546gb EEPROM

    Abstract: No abstract text available
    Text: 82546GB Dual Port Gigabit Ethernet Controller Networking Silicon Datasheet Product Features • ■ ■ PCI/PCI-X — PCI-X Revision 1.0a support for frequencies up to 133 MHz — Multi-function PCI device — PCI Revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 MHz and


    Original     		82546GB 32-bit 64-bit 82546GB intel 82546gb EEPROM PDF

    Untitled

    Abstract: No abstract text available
    Text: ISPLSI 8840 In-System Programmable SuperBIG High Density PLD • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 5V Power Supply 45,000 PLD Gates/840 Macrocells Up to 312 I/O Pins Supporting 3.3V/5V I/O 1152 Registers High-Speed Global and Big Fast Megablock BFM Interconnect


    Original     		Gates/840 20-Macrocell ispLSI8000 IspLSI8840 38-to38 IspLSI8840 PDF

    pn sequence generator using d flip flop

    Abstract: pn sequence generator using jk flip flop FULL SUBTRACTOR using 41 MUX full subtractor circuit using xor and nand gates verilog code for 16 bit carry select adder verilog code pipeline ripple carry adder verilog code for jk flip flop vhdl for 8 bit lut multiplier ripple carry adder synchronous updown counter using jk flip flop Mux 1x8 74
    Text: 0373f.fm Page 1 Tuesday, May 25, 1999 8:59 AM Table of Contents Component Generators Introduction .3 AT40K Co-processor FPGAs .4


    Original     		0373f AT40K pn sequence generator using d flip flop pn sequence generator using jk flip flop FULL SUBTRACTOR using 41 MUX full subtractor circuit using xor and nand gates verilog code for 16 bit carry select adder verilog code pipeline ripple carry adder verilog code for jk flip flop vhdl for 8 bit lut multiplier ripple carry adder synchronous updown counter using jk flip flop Mux 1x8 74 PDF

    signal path designer

    Abstract: isplsi architecture
    Text: ispLSI : A Multiple Function Solution these cases, using sockets may be necessary to minimize manufacturing problems for the programmable devices. All Lattice ispLSI devices feature In-System Programmability ISP , so removing devices from the board is not necessary if reprogramming is required.


    Original     		1-800-LATTICE signal path designer isplsi architecture PDF

    PC82545GM

    Abstract: No abstract text available
    Text: 82545GM Gigabit Ethernet Controller Networking Silicon Datasheet Product Features • ■ ■ PCI/PCI-X — PCI-X Revision 1.0a support for frequencies up to 133 MHz — Multi-function PCI device — PCI Revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 MHz and


    Original     		82545GM 32-bit 64-bit PC82545GM PDF

    Untitled

    Abstract: No abstract text available
    Text: 82545GM Gigabit Ethernet Controller Networking Silicon Datasheet Product Features • ■ ■ PCI/PCI-X — PCI-X Revision 1.0a support for frequencies up to 133 MHz — Multi-function PCI device — PCI Revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 MHz and


    Original     		82545GM 32-bit 64-bit PDF

    PC82545GM

    Abstract: RC82545
    Text: 82545GM Gigabit Ethernet Controller Networking Silicon Datasheet Product Features • PCI/PCI-X — PCI-X Revision 1.0a support for frequencies up to 133 MHz — Multi-function PCI device — PCI Revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 MHz and


    Original     		82545GM 32-bit 64-bit PC82545GM RC82545 PDF

    Untitled

    Abstract: No abstract text available
    Text: 82545GM Gigabit Ethernet Controller Networking Silicon Datasheet Revision 1.5 June 2005 Revision History Revision Date 1.0 Mar 2003 Description Initial release. Removed Confidential Status. 1.1 Nov 2003 Modified power specification tables in Section 4.0. Added a ball pad dimension drawing for the 82545GM device in Section 5.0.


    Original     		82545GM 82545GM PDF

    Signal Path Designer

    Abstract: altera ep910i
    Text: Classic EPLD Family M ay 1999 ver. ;> Features D ata S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements


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    Signal Path Designer

    Abstract: No abstract text available
    Text: Classic EPLD Family M ay 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith non-volatile EPROM configuration elements


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    Signal Path Designer

    Abstract: No abstract text available
    Text: Classic EPLD Family J a n u a ry 1998. ver. Features Data Sheet 4 * • ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features EP610 EP610I EP910 EP910I EP1810 300 450 900 Macrocells 16 24 48 Maximum user I/O pins 22 38 64 Feature Usable gates Altera Corporation


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    Untitled

    Abstract: No abstract text available
    Text: NECES001 C P20K 0 .8 -M IC R O N NEC Electronics Inc. fpgas February 1993 Description Figure 1. CP20K FPGAs NEC Electronics Inc. and Crosspoint Solutions, Inc. have joined forces to offer to system designers an expedient way to prototype in Field Programmable Gate Arrays


    OCR Scan     		NECES001 CP20K RAM8x16* RAM16x16* RAM32x16* RAM8x32* 16x32* RAM32x4* RAM64x4* PDF

    FC SUFFIX altera

    Abstract: No abstract text available
    Text: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates


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    mx41 plc

    Abstract: 2-BIT Full-Adder CP20K NEC lcd inverter schematic NEC CP20K FPGA nec cmos CLS199 LDPC Decoder vhdl RAM64X4 9020 8pin
    Text: MAR i o 1983 C P20K 0 .8 -M IC R O N fp g a s NEC Electronics Inc. February 1993 Description Figure 1. CP20K FPGAs NEC Electronics Inc. and Crosspoint Solutions, Inc. have joined forces to offer to system designers an expedient way to prototype in Field Program m able Gate Arrays


    OCR Scan     		CP20K mx41 plc 2-BIT Full-Adder NEC lcd inverter schematic NEC CP20K FPGA nec cmos CLS199 LDPC Decoder vhdl RAM64X4 9020 8pin PDF

    EPM5130

    Abstract: EPM5016
    Text: E P M 5016 to E P M 5192 E PLD s High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.


    OCR Scan     		20-pin 100-pin 15-ns EPM5130 EPM5016 PDF

    ALTERA MAX 5000

    Abstract: EPM5016 jlcc 32 R program EPM5032 epm5128a ALTERA MAX 5000 programming
    Text: M A X 5 0 00/EPS464 Programmable Logic Device Family Data Sheet August 1993, ver. 1 □ Features □ □ □ □ □ □ □ □ □ Advanced M ultiple Array M atrix MAX 5000/E P S464 architecture com bining speed and ease-of-use of PAL devices with density of


    OCR Scan     		00/EPS464 5000/E 20-pin 100-pin 65-micron 12-ns ALTED001 ALTERA MAX 5000 EPM5016 jlcc 32 R program EPM5032 epm5128a ALTERA MAX 5000 programming PDF

    Untitled

    Abstract: No abstract text available
    Text: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP1810 900 300 450 16 24 48 Maximum user I/O pins 22 38 64 tp D n s 10 12 20 100 76.9 50 f CNT A-DS-CLASSIC-03 EP910 &


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    epm5064

    Abstract: EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter
    Text: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 F e a tu r e s. Data Sheet * • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array Matrix MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays


    OCR Scan     		28-pin 100-pin 15-ns 84-Pin EPM5192 epm5064 EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter PDF